132 lines
7.1 KiB
TeX
132 lines
7.1 KiB
TeX
\chapter*{Conclusion}
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\addcontentsline{toc}{chapter}{Conclusion}
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During this manuscript, we explored the main bottlenecks that arise while
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analyzing the low-level performance of a microkernel:
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\begin{itemize}
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\item frontend bottlenecks ---~the processor's frontend is unable to
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saturate the backend with instructions (\autoref{chap:palmed});
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\item backend bottlenecks ---~the backend is saturated with instructions
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from the frontend and is unable to process them fast enough
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(\autoref{chap:frontend});
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\item dependencies bottlenecks ---~data dependencies between instructions
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prevent the backend from being saturated; the latter is stalled
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awaiting previous results (\autoref{chap:staticdeps}).
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\end{itemize}
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We also conducted in \autoref{chap:CesASMe} a systematic comparative study of a
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variety of state-of-the-art code analyzers.
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\bigskip{}
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State-of-the-art code analyzers such as \llvmmca{} or \uica{} already
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boast a good accuracy. Both of these tools ---~and most of the others also~---
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are however based on models obtained by various degrees of manual
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investigation, and cannot be adapted without further manual effort to future
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or uncharted microprocessors.
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The field of microarchitectural models for code
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analysis emerged with fundamentally manual methods, such as Agner Fog's tables.
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Such tables, however, may now be produced in a more automated way using
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\uopsinfo{} ---~at least for certain microarchitectures; \pmevo{} pushes
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further in this direction by automatically computing a frontend model from
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benchmarks ---~but still has trouble scaling to a full instruction set. In its
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own way, \ithemal{}, a machine-learning based approach, could also be
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considered automated ---~yet, it still requires a large training set for the
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intended processor, which must be at least partially crafted manually.
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This trend towards model automation seems only natural as new
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microarchitectures keep appearing, while new ISAs such as ARM reach the
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supercomputer area.
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\medskip{}
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We investigated this direction by exploring the three major bottlenecks
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mentioned earlier in the perspective of providing fully-automated,
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benchmarks-based models for each of them. Optimally, these models should be
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generated by simply executing a program on a machine running on top of the
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targeted microarchitecture.
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\begin{itemize}
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\item We contributed to \palmed{}, a framework able to extract a
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port-mapping of a processor, serving as a backend model.
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\item We manually extracted a frontend model for the Cortex A72 processor.
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We believe that the foundation of our methodology works on most
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processors. To this end, we provide a parametric model that may serve
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as a scaffold for future works willing to build an automatic frontend
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model. Some parameters of this model must however still
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be investigated, and their relative importance evaluated.
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\item We provided with \staticdeps{} a method to to extract data
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dependencies between instructions. It is able to detect
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\textit{loop-carried} dependencies (dependencies that span across
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multiple loop iterations), as well as \textit{memory-carried}
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dependencies (dependencies based on reading at a memory address written
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by another instruction). While the former is widely implemented, the
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latter is, to the best of our knowledge, an original contribution. We
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bundled this method in a processor-independent tool, based on semantics
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of the ISA provided by \valgrind{}, which supports a variety of ISAs.
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\end{itemize}
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\bigskip{}
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We evaluated independently these three models, each of them providing
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satisfactory results: \palmed{} is competitive with the state of the art, with
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the advantage of being automatic; our frontend model significantly improves a
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backend model's accuracy and our dependencies model significantly improves
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\uica{}'s results, while being consistent with a dynamic dependencies analysis.
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Finally, in the pre-conclusive chapter \nameref{chap:wrapping_up}, we loosely
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combine our three pieces of code analyzer model into a very simple full model,
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returning the maximal prediction from the three major bottleneck analyzers.
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While this simplistic model would certainly benefit from a more integrated
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approach, our results already significantly surpass \llvmmca{}, one of the very
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few state-of-the-art tools on ARM processors.
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\bigskip{}
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We also identified multiple weaknesses in the current state of the art from our
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comparative experiments with \cesasme{}.
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\smallskip{}
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First, none of the state-of-the-art tools have a good support for dependencies
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across memory. Such dependencies were present in about a third of \cesasme{}'s
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benchmark set. While we built this benchmark set aiming for representative
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data, there is no clear evidence that these dependencies are so strongly
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present in the codes analyzed in real usecases. We however believe that such
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cases regularly occur, and we also saw that the performance of code analyzers
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drops sharply in their presence.
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\smallskip{}
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We also found the bottleneck prediction offered by some code analyzers still
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very uncertain. In our experiments, the tools disagreed more often than not on
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the presence or absence of a bottleneck, with no outstanding tool; we are thus
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unable to conclude on the relative performance of tools on this aspect. On the
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other hand, sensitivity analysis, as implemented \eg{} by \gus{}, seems a
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theoretically sound way to evaluate the presence or absence of a bottleneck in
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a microkernel; it is, however, prohibitively slow for many usecases. In this
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respect, a study of code analyzers' predictions against results from
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sensitivity analysis would certainly bring more conclusive results.
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\smallskip{}
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Finally, we observed on \bhive{}'s results the effects of a \emph{lack of
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context} for an analysis. \bhive{} measures a real execution, on real hardware,
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of a kernel; as such, it yields excellent accuracy in many cases, with a median
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error of about 8\%. Yet, it still lacks in accuracy in many other cases, with
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its third quartile (23\%) above \uica{} or \iaca{}'s median result (about
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18\%), and far-reaching outliers bringing its mean error on-par with \uica{}'s.
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Indeed, what precedes a loop nest and the real values present in registers
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impact the performance of the loop nest. The effects can be of fairly high
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level, such as pointer aliasing, leading to false positives or negatives in
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dependency detections. They can also be of a microarchitectural level, such as
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the observable performance loss of memory accesses ---~even with cache hits~---
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when memory reads cross a cache line boundary.
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This lack of context incurs a significant loss of accuracy for
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static analyzers, as we saw in \autoref{ssec:bhive_errors} that the same
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instruction, depending on its registers' values, can be twice as slow even
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without aliasing, or 19 times slower upon aliasing. With \cesasme{}, we sketch
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the embryo of a solution, with a simple and fast pass of dynamic analysis
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through instrumentation, gathering data for a subsequent pass of static
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analysis. Such a method might help recreating the context needed for an
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accurate analysis.
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