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c5eabf6997
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2188c29b51
| Author | SHA1 | Date | |
|---|---|---|---|
| 2188c29b51 | |||
| eb1bc1d602 | |||
| 2f68882783 | |||
| 63acbb7634 |
8 changed files with 312 additions and 111 deletions
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@ -16,72 +16,68 @@
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\begin{column}{0.62\textwidth}
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\begin{tightitemize}{0pt}
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\begin{itemize}
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\item \alert{Frontend:} \uops{} not issued fast enough;
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issuing faster would speed up computation;
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\item \alert{Frontend:} \uops{} not issued fast enough
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\bigskip
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\item \alert{Backend:} saturated execution units; adding
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more units would speed up computation;
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\item \alert{Backend:} saturated execution units
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\bigskip
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\item \alert{Dependencies:} computation is stalled waiting
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for previous results; removing data dependencies would
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speed up computation.
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for previous results
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\end{itemize}
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\end{tightitemize}
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\end{column}
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\end{columns}
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\end{frame}
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\begin{frame}{Dependencies and the ROB}
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\begin{columns}
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\begin{column}{0.35\textwidth}
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\begin{center}
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\includegraphics[width=\textwidth]{cpu_frontend.svg}
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\end{center}
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\end{column}
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\hfill
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\begin{column}{0.64\textwidth}
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\begin{tightitemize}{0pt}
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\begin{itemize}
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\item Dependencies can stall execution
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\item Maybe instructions further down can be executed right now?
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\end{itemize}
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\begin{center}
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\textbf{\alert{$\to$ Out-of-Order CPUs}}
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\end{center}
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\begin{itemize}
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\item ROB: circular buffer of \uops{}
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\item First possible instruction is issued
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\end{itemize}
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\end{tightitemize}
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\end{column}
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\end{columns}
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\end{frame}
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%\begin{frame}{Dependencies and the ROB}
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% \begin{columns}
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% \begin{column}{0.35\textwidth}
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% \begin{center}
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% \includegraphics[width=\textwidth]{cpu_frontend.svg}
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% \end{center}
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% \end{column}
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% \hfill
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% \begin{column}{0.64\textwidth}
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% \begin{tightitemize}{0pt}
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% \begin{itemize}
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% \item Dependencies can stall execution
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% \item Maybe instructions further down can be executed right now?
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% \end{itemize}
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% \begin{center}
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% \textbf{\alert{$\to$ Out-of-Order CPUs}}
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% \end{center}
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% \begin{itemize}
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% \item ROB: circular buffer of \uops{}
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% \item First possible instruction is issued
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% \end{itemize}
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% \end{tightitemize}
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% \end{column}
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% \end{columns}
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%\end{frame}
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\begin{frame}{How do we get insights from this complex system?}
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\textbf{Hardware counters}
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\begin{itemize}
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\item Built-in hardware, counters gathered at runtime
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\item Very accurate
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\item Available data varies from model to model
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\item May not even be available at all
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\end{itemize}
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%\begin{frame}{How do we get insights from this complex system?}
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% \textbf{Hardware counters}
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% \begin{itemize}
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% \item Built-in hardware, counters gathered at runtime
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% \item Very accurate
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% \item Available data varies from model to model
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% \item May not even be available at all
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% \end{itemize}
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%
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% \textbf{Simulation?}
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% \begin{itemize}
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% \item A modern CPU is \alert{$\sim$\,100e9 transistors}: very complex
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% models!
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% \item Very expensive, even for manufacturers for design validation
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% \item CPU design is industrial secret $\leadsto$ not available anyway
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% \item \ldots{}\ie{} not feasible.
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% \end{itemize}
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%\end{frame}
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\textbf{Simulation?}
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\begin{frame}{Code analyzers}
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\begin{itemize}
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\item A modern CPU is \alert{$\sim$\,100e9 transistors}: very complex
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models!
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\item Very expensive, even for manufacturers for design validation
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\item CPU design is industrial secret $\leadsto$ not available anyway
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\item \ldots{}\ie{} not feasible.
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\end{itemize}
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\end{frame}
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\begin{frame}{Enter code analyzers}
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\begin{itemize}
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\item Tools that predict performance of a piece of assembly code on a
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given CPU
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\item That predict performance of a piece of assembly
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\item Features microarchitectural models
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\item Most often static analyzers
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\item Predict at least the \emph{reverse-throughput} $\cyc{\kerK}$ of a
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@ -127,5 +123,6 @@
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\begin{frame}{When I started my PhD\ldots}
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\centering
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\includegraphics[height=0.9\textheight]{patate_placeholder.jpg}
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%\includegraphics[height=0.9\textheight]{patate_placeholder.jpg}
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\includegraphics[height=0.9\textheight]{sota_potato.svg}
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\end{frame}
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@ -138,6 +138,17 @@ Gus & 0.00 & 20.37 & 30.59 & 0.82 & 188.04 \\
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\textbf{Crucial difference:}
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\end{center}
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\begin{minipage}[t]{0.47\textwidth}
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\begin{center}
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\textbf{\color{red}Bad}
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\end{center}
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\vspace{-1em}
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\begin{lstlisting}[language={[ANSI]C}]
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for(c3)
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tmp[c1] += A[c1][c3] * x[c3];
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\end{lstlisting}
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\end{minipage}
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\hfill\vrule\hfill
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\begin{minipage}[t]{0.47\textwidth}
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\begin{center}
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\textbf{\color[HTML]{008f0c}Good}
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@ -147,16 +158,6 @@ Gus & 0.00 & 20.37 & 30.59 & 0.82 & 188.04 \\
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for(c3)
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A[c1][c3] += u1[c1] * v1[c3]
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+ u2[c1] * v2[c3];
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\end{lstlisting}
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\end{minipage}\hfill\vrule\hfill
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\begin{minipage}[t]{0.47\textwidth}
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\begin{center}
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\textbf{\color{red}Bad}
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\end{center}
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\vspace{-1em}
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\begin{lstlisting}[language={[ANSI]C}]
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for(c3)
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tmp[c1] += A[c1][c3] * x[c3];
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\end{lstlisting}
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\end{minipage}
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@ -70,6 +70,14 @@ add %rbx, (%rax)
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\item Loop-carried: luckily, ROB is finite and small
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\end{itemize}
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\end{minipage}
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\pause{}
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\bigskip
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\begin{center}
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\textbf{Hypothesis:} pointers from context \alert{do not
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alias}.\\
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Compilers prefer passing a single pointer.
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\end{center}
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\end{frame}
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@ -142,35 +150,36 @@ int fibo(int* F, int n) {
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\footnotesize
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\begin{tabular}{c c c c c c c c c l}
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\toprule
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\textbf{Before} & \multicolumn{2}{c}{\textbf{Registers}} &&
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\textbf{After} & \multicolumn{2}{c}{\textbf{Registers}} &&
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\multicolumn{5}{c}{\textbf{Memory}} & \textbf{Dep}\\
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\textbf{instr} & \reg{rax} & \reg{edx}
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&& \texttt{100} & \texttt{104} & \texttt{108} & \texttt{112} & \texttt{116} & \\
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\midrule
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0,0 & \unk& \unk&& \unk & \unk & \unk & \unk & \unk & \\
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\pause{}
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0,1 & 100 & 200 && 200\h& \unk & \unk & \unk & \unk & \\
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\pause{}
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0,2 & 100 & 376 && 200 & 176\h& \unk & \unk & \unk & \\
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\pause{}
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0,3 & 100 & 376 && 200 & 176 & 376\w& \unk & \unk & \\
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\pause{}
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0,4 & \alert{104} & 376 && 200 & 176 & 376 & \unk & \unk & \\
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0,5 & 100 & 376 && 200 & 176 & 376 & \unk & \unk & \\
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Start & \unk& \unk&& \unk & \unk & \unk & \unk & \unk & \\
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\midrule
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\pause{}
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1,1 & 104 & \alert{176} && 200 & 176\h& 376 & \unk & \unk & \\
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0,0 & 100 & 200 && 200\h& \unk & \unk & \unk & \unk & \\
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\pause{}
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1,2 & 104 & \alert{552} && 200 & 176 & 376\h& \unk & \unk & \dep{-1,3}\\
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0,1 & 100 & 376 && 200 & 176\h& \unk & \unk & \unk & \\
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\pause{}
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1,3 & 104 & 552 && 200 & 176 & 376 & 552\w& \unk & \\
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0,2 & 100 & 376 && 200 & 176 & 376\w& \unk & \unk & \\
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\pause{}
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0,3 & \alert{104} & 376 && 200 & 176 & 376 & \unk & \unk & \\
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0,4 & 100 & 376 && 200 & 176 & 376 & \unk & \unk & \\
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\midrule
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\pause{}
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2,1 & 108 & \alert{376} && 200 & 176 & 376\h& 552 & \unk & \dep{-2,3}\\
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1,0 & 104 & \alert{176} && 200 & 176\h& 376 & \unk & \unk & \\
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\pause{}
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2,2 & 108 & \alert{928} && 200 & 176 & 376 & 552\h& \unk & \dep{-1,3}\\
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1,1 & 104 & \alert{552} && 200 & 176 & 376\h& \unk & \unk & \dep{-1,2}\\
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\pause{}
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2,3 & 108 & 928 && 200 & 176 & 376 & 552 & 928\w &\\
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1,2 & 104 & 552 && 200 & 176 & 376 & 552\w& \unk & \\
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\midrule
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\pause{}
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2,0 & 108 & \alert{376} && 200 & 176 & 376\h& 552 & \unk & \dep{-2,2}\\
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\pause{}
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2,1 & 108 & \alert{928} && 200 & 176 & 376 & 552\h& \unk & \dep{-1,2}\\
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\pause{}
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2,2 & 108 & 928 && 200 & 176 & 376 & 552 & 928\w &\\
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\bottomrule{}
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\end{tabular}
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\end{minipage}\hfill
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@ -7,7 +7,7 @@
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@ -23,12 +23,12 @@
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After Width: | Height: | Size: 11 KiB |
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@ -43,6 +43,27 @@ CORSE team}}}
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|||
\importchapter{50_staticdeps}
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||||
\importchapter{60_a72combined}
|
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|
||||
\begin{frame}{Conclusion}
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\begin{itemize}
|
||||
\item \alert{\cesasme{}}: a framework to faithfully compare code analyzers;
|
||||
\begin{itemize}
|
||||
\item used to compare SotA analyzers
|
||||
\item reveals dependencies through memory as clear weakness
|
||||
\end{itemize}
|
||||
\item \alert{\staticdeps{}}: a static analyzer to extract dependencies,
|
||||
incl.\@ through memory
|
||||
\item A manual \alert{frontend model} for the Cortex A72 ARM processor
|
||||
\begin{itemize}
|
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\item parametric model for future works on the frontend
|
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\item partially automated
|
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\end{itemize}
|
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\medskip
|
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|
||||
\item A loosely \alert{combined model} including those,
|
||||
\alert{outperforming} (manual) \alert{SotA}.
|
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\end{itemize}
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\end{frame}
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\begin{frame}[standout]
|
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\Large{}Questions?
|
||||
\end{frame}
|
||||
|
|
|
|||
Loading…
Reference in a new issue