Hack through Foundations (lightly) to reduce time
|
@ -16,72 +16,68 @@
|
|||
\begin{column}{0.62\textwidth}
|
||||
\begin{tightitemize}{0pt}
|
||||
\begin{itemize}
|
||||
\item \alert{Frontend:} \uops{} not issued fast enough;
|
||||
issuing faster would speed up computation;
|
||||
\item \alert{Frontend:} \uops{} not issued fast enough
|
||||
\bigskip
|
||||
|
||||
\item \alert{Backend:} saturated execution units; adding
|
||||
more units would speed up computation;
|
||||
\item \alert{Backend:} saturated execution units
|
||||
\bigskip
|
||||
|
||||
\item \alert{Dependencies:} computation is stalled waiting
|
||||
for previous results; removing data dependencies would
|
||||
speed up computation.
|
||||
for previous results
|
||||
\end{itemize}
|
||||
\end{tightitemize}
|
||||
\end{column}
|
||||
\end{columns}
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}{Dependencies and the ROB}
|
||||
\begin{columns}
|
||||
\begin{column}{0.35\textwidth}
|
||||
\begin{center}
|
||||
\includegraphics[width=\textwidth]{cpu_frontend.svg}
|
||||
\end{center}
|
||||
\end{column}
|
||||
\hfill
|
||||
\begin{column}{0.64\textwidth}
|
||||
\begin{tightitemize}{0pt}
|
||||
\begin{itemize}
|
||||
\item Dependencies can stall execution
|
||||
\item Maybe instructions further down can be executed right now?
|
||||
\end{itemize}
|
||||
\begin{center}
|
||||
\textbf{\alert{$\to$ Out-of-Order CPUs}}
|
||||
\end{center}
|
||||
\begin{itemize}
|
||||
\item ROB: circular buffer of \uops{}
|
||||
\item First possible instruction is issued
|
||||
\end{itemize}
|
||||
\end{tightitemize}
|
||||
\end{column}
|
||||
\end{columns}
|
||||
\end{frame}
|
||||
%\begin{frame}{Dependencies and the ROB}
|
||||
% \begin{columns}
|
||||
% \begin{column}{0.35\textwidth}
|
||||
% \begin{center}
|
||||
% \includegraphics[width=\textwidth]{cpu_frontend.svg}
|
||||
% \end{center}
|
||||
% \end{column}
|
||||
% \hfill
|
||||
% \begin{column}{0.64\textwidth}
|
||||
% \begin{tightitemize}{0pt}
|
||||
% \begin{itemize}
|
||||
% \item Dependencies can stall execution
|
||||
% \item Maybe instructions further down can be executed right now?
|
||||
% \end{itemize}
|
||||
% \begin{center}
|
||||
% \textbf{\alert{$\to$ Out-of-Order CPUs}}
|
||||
% \end{center}
|
||||
% \begin{itemize}
|
||||
% \item ROB: circular buffer of \uops{}
|
||||
% \item First possible instruction is issued
|
||||
% \end{itemize}
|
||||
% \end{tightitemize}
|
||||
% \end{column}
|
||||
% \end{columns}
|
||||
%\end{frame}
|
||||
|
||||
\begin{frame}{How do we get insights from this complex system?}
|
||||
\textbf{Hardware counters}
|
||||
\begin{itemize}
|
||||
\item Built-in hardware, counters gathered at runtime
|
||||
\item Very accurate
|
||||
\item Available data varies from model to model
|
||||
\item May not even be available at all
|
||||
\end{itemize}
|
||||
%\begin{frame}{How do we get insights from this complex system?}
|
||||
% \textbf{Hardware counters}
|
||||
% \begin{itemize}
|
||||
% \item Built-in hardware, counters gathered at runtime
|
||||
% \item Very accurate
|
||||
% \item Available data varies from model to model
|
||||
% \item May not even be available at all
|
||||
% \end{itemize}
|
||||
%
|
||||
% \textbf{Simulation?}
|
||||
% \begin{itemize}
|
||||
% \item A modern CPU is \alert{$\sim$\,100e9 transistors}: very complex
|
||||
% models!
|
||||
% \item Very expensive, even for manufacturers for design validation
|
||||
% \item CPU design is industrial secret $\leadsto$ not available anyway
|
||||
% \item \ldots{}\ie{} not feasible.
|
||||
% \end{itemize}
|
||||
%\end{frame}
|
||||
|
||||
\textbf{Simulation?}
|
||||
\begin{frame}{Code analyzers}
|
||||
\begin{itemize}
|
||||
\item A modern CPU is \alert{$\sim$\,100e9 transistors}: very complex
|
||||
models!
|
||||
\item Very expensive, even for manufacturers for design validation
|
||||
\item CPU design is industrial secret $\leadsto$ not available anyway
|
||||
\item \ldots{}\ie{} not feasible.
|
||||
\end{itemize}
|
||||
\end{frame}
|
||||
|
||||
\begin{frame}{Enter code analyzers}
|
||||
\begin{itemize}
|
||||
\item Tools that predict performance of a piece of assembly code on a
|
||||
given CPU
|
||||
\item That predict performance of a piece of assembly
|
||||
\item Features microarchitectural models
|
||||
\item Most often static analyzers
|
||||
\item Predict at least the \emph{reverse-throughput} $\cyc{\kerK}$ of a
|
||||
|
|
|
@ -7,7 +7,7 @@
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