30 lines
1.8 KiB
TeX
30 lines
1.8 KiB
TeX
The state-of-the-art tools presented in \autoref{sec:sota} are already capable
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of good microarchitectural analysis and predictions in many aspects. One thing,
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however, that we found lacking, was a generic method to obtain a model for a
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given microarchitecture. Indeed, while \eg{} \iaca{} and \uopsinfo{} are
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performant and quite exhaustive models of Intel's x86-64 implementations, they
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are restricted to Intel CPUs ---~and few others for \uopsinfo{}. These models
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were, at least up to a point, handcrafted. While \iaca{} is based on insider's
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knowledge from Intel (and thus would not work for \eg{} AMD), \uopsinfo{}'s
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method is based on specific hardware counters and handpicked instructions with
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specific properties.
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While these methods provide great models, they only apply to the covered CPUs.
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In the meantime, many new CPUs are released, some for commercial applications,
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some others for specific domains, fostering less attention from
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microarchitecture specialists. For those CPUs not covered by these specific
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models, a generic method to extract a model from running benchmarks on a
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processor could be beneficial to performance debuggers.
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While \pmevo{}~\cite{PMEvo} laid a first milestone in this direction (see
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\autoref{sec:sota}), their methodology struggles to scale to the full
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instruction set of a CPU, as we show in this chapter. To this end,
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\nderumig{} designed \palmed{} during his PhD work. Although the theoretical
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work at the core of \palmed{} is his, I contributed significantly to this
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project during the first period of my own PhD.
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In this chapter, sections~\ref{sec:palmed_resource_models}
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through~\ref{sec:palmed_pipedream} describe \palmed{}, and present what is
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mostly not my own work, but introduce important concepts for this manuscript.
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Sections~\ref{sec:benchsuite_bb} and later describe my own work on this
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project.
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