63 lines
3.2 KiB
TeX
63 lines
3.2 KiB
TeX
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\section{A dive into processors' microarchitecture}
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A modern computer can roughly be broken down into a number of functional parts:
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a processor, a general-purpose computation unit; accelerators, such
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as GPUs, computation units specialized on specific tasks; memory, both volatile
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but fast (RAM) and persistent but slower (SSD, HDD); hardware specialized for
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interfacing, such as networks cards or USB controllers; power supplies,
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responsible for providing smoothed, adequate electric power to the previous
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components.
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This manuscript will largely focus on the processor. While some of the
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techniques described here might possibly be used for accelerators, we did not
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experiment in this direction, nor are we aware of efforts in this direction.
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\subsection{High-level abstraction of processors}
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A processor, in its coarsest view, is simply a piece of hardware that can be
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fed with a flow of instructions, which will, each after the other, modify the
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machine's internal state.
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The processor's state, the available instructions themselves and their
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effect on the state are defined by an \emph{Instruction Set Architecture}, or
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ISA\@. These instructions are represented, at a human-readable level, by
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\emph{assembly code}, but are transcribed, or \emph{assembled}, to a binary
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representation in order to be fed to the processor.
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This state, generally, is composed of a small number of \emph{registers}, small
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pieces of memory on which the processor can directly operate ---~to perform
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arithmetic operations, index the main memory, etc. It is also composed of the
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whole memory hierarchy, including the persistent memory, the main memory
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(usually RAM) and the hierarchy of caches between the processor and the main
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memory. This state can also be extended to encompass external effects, such as
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networks communication, peripherals, etc.
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The way an ISA is implemented, in order for the instructions to alter the state
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as specified, is called a microarchitecture. Many microarchitectures can
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implement the same ISA, as it is the case for instance with the x86-64 ISA,
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implemented both by Intel and AMD, each with multiple generations, which
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translates into multiple microarchitectures.
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\subsection{Microarchitectures}
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While many different ISAs are available and used, and even many more
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microarchitectures are industrially implemented and widely distributed, some
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generalities still hold for the vast majority of processors found in commercial
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or server-grade computers. Such a generic view is obviously an approximation
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and will miss many details and specificities; it should, however, be sufficient
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for the purposes of this manuscript.
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A microarchitecture can be broken down into a few functional blocks, shown in
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\qtodo{fig}, roughly amounting to a \emph{frontend}, a \emph{backend}, a
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\emph{register file} and multiple \emph{data caches}.
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\medskip{}
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\paragraph{Frontend.} The frontend is responsible for fetching the flow of
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instruction bytes to be executed, decode them into instructions, and dispatch
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them to execution units.
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\paragraph{Backend.} The backend is composed of \emph{execution ports}, which
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act as gateways to the actual \emph{execution units}. Those units are
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responsible for the actual computations made by the processor.
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