49 lines
2.7 KiB
TeX
49 lines
2.7 KiB
TeX
The usual reverse-engineering methods for CPU models usually make abundant use
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of hardware counters ---~and legitimately so, as they are the natural and
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accurate way to obtain insight on the internals of a CPU\@. Such methods
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include, among others, the optimisation guides from Agner Fog~\cite{AgnerFog},
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as well as \uopsinfo{}~\cite{uopsinfo} and \uica{}'s~\cite{uica} approach to
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respectively model the CPU's back- and front-end. In \autoref{chap:palmed}, we
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introduced Palmed, whose main goal is to automatically produce port-mappings of
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CPUs without assuming the presence of specific hardware counters.
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\smallskip{}
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The ARM architectures occupy a growing space in the global computing ecosystem.
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They are already pervasive among the embedded and mobile devices, with most
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mobile phones featuring an ARM CPU~\cite{arm_mobile}. Processors based on ARM
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are emerging in datacenters and supercomputers: the Fugaku supercomputer
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---~considered the fastest supercomputer in the world by the TOP500
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ranking~\cite{fugaku_top500}~--- runs on ARM-based CPUs~\cite{fugaku_arm}, the
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MareNostrum 4 supercomputer has an ARM-based cluster~\cite{marenostrum4_arm}.
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Yet, the ARM ecosystem is still lacking in performance debugging tooling. While
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\llvmmca{} supports ARM, it is one of the only few: \iaca{}, made by Intel, is
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not supported ---~and will never be, as it is end-of-life~---; \uica{} is
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focused on Intel architectures, and cannot be easily ported as it heavily
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relies on reverse engineering specific to Intel, and enabled by specific
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hardware counters; Intel \texttt{VTune}, a commonly used profiling performance
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analysis tool, supports only x86-64.
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\smallskip{}
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In this context, modelling an ARM CPU ---~the Cortex A72~--- with \palmed{}
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seemed to be an important goal, especially meaningful as this particular CPU
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only has very few hardware counters. However, it yielded only mixed results, as
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we will see in \autoref{sec:a40_eval}.
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\bigskip{}
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In this chapter, we show that a major cause of imprecision in these results is
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the absence in \palmed{} of a frontend model. We manually model the Cortex A72
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frontend to compare a raw \palmed{}-generated model, to one naively augmented
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with a frontend model.
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While this chapter only documents a manual approach, we view it as a
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preliminary work towards an automation of the synthesis of a model that stems
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from benchmarks data, in the same way that \palmed{} synthesises a backend
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model. In this direction, we propose in \autoref{sec:frontend_parametric_model}
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a generic, parametric frontend that, we expect, could be used with good results
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on many architectures. We also offer methodologies that we expect to be able to
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automatically fill some of the parameters of this model for an arbitrary
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architecture.
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