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Foundations: slightly more writeup

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Théophile Bastian 2023-11-03 17:47:11 +01:00
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manuscrit/20_foundations/10_cpu_arch.tex
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@ -67,14 +67,23 @@ for the purposes of this manuscript.
A microarchitecture can be broken down into a few functional blocks, shown in A microarchitecture can be broken down into a few functional blocks, shown in
\autoref{fig:cpu_big_picture}, roughly amounting to a \emph{frontend}, a \emph{backend}, a \autoref{fig:cpu_big_picture}, roughly amounting to a \emph{frontend}, a \emph{backend}, a
\emph{register file} and multiple \emph{data caches}. \emph{register file}, multiple \emph{data caches} and a \emph{retire buffer}.
\medskip{} \medskip{}
\paragraph{Frontend.} The frontend is responsible for fetching the flow of \paragraph{Frontend.} The frontend is responsible for fetching the flow of
instruction bytes to be executed, decode them into instructions, and dispatch instruction bytes to be executed, break it down into operations executable by
them to execution units. the backend and issue them to execution units.
\paragraph{Backend.} The backend is composed of \emph{execution ports}, which \paragraph{Backend.} The backend is composed of \emph{execution ports}, which
act as gateways to the actual \emph{execution units}. Those units are act as gateways to the actual \emph{execution units}. Those units are
responsible for the actual computations made by the processor. responsible for the actual computations made by the processor.
\paragraph{Register file.} The register file holds the processor's registers,
on which computations are made.
\paragraph{Data caches.} The cache hierarchy (usually L1, L2 and L3) caches
data rows from the main memory, whose access latency would slow computation
down by several orders of magnitude if it was accessed directly. Usually, the
L1 cache resides directly in the computation core, while the L2 and L3 caches
are shared between multiple cores.