RISC-V vector: correct references
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@ -258,4 +258,6 @@ only one such instruction per two cycles. Even in this case, there are clear
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efficiency benefits: while there is no real gain in the backend, the frontend
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efficiency benefits: while there is no real gain in the backend, the frontend
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has only one instruction to decode, rename, etc., greatly alleviating frontend
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has only one instruction to decode, rename, etc., greatly alleviating frontend
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pressure. This is for instance the case of the implementation of the
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pressure. This is for instance the case of the implementation of the
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RISC-V~\cite{riscv_isa} vector extension, \qtodo{ref Filippo Mantovani}
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RISC-V~\cite{riscv_isa} vector extension, supporting up to 256 double-precision
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floats in a single operation, while the hardware supports far less in one
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cycle~\cite{filippo_riscv_vector, filippo_acaces23}.
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@ -188,3 +188,18 @@
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pages={1--32},
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pages={1--32},
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year={2011}
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year={2011}
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}
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}
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@inproceedings{filippo_riscv_vector,
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title={Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study},
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author={Mantovani, Filippo and Vizcaino, Pablo and Banchelli, Fabio and Garcia-Gasulla, Marta and Ferrer, Roger and Ieronymakis, Georgios and Dimou, Nikolaos and Papaefstathiou, Vassilis and Labarta, Jesus},
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booktitle={International Conference on High Performance Computing},
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pages={526--537},
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year={2023},
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organization={Springer}
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}
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@misc{filippo_acaces23,
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author={Mantovani, Filippo},
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year={2023},
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month={July},
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howpublished={Private communication during the ACACES summer school},
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}
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