A72: start writeup
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The usual reverse-engineering methods for CPU models usually make abundant use
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of hardware counters ---~and legitimately so, as they are the natural and
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accurate way to obtain insight on the internals of a CPU\@. Such methods
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include, among others, the optimisation guides from Agner Fog~\cite{AgnerFog},
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as well as \uopsinfo{}~\cite{uopsinfo} and \uica{}'s~\cite{uica} approach to
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respectively model the CPU's back- and front-end. In \autoref{chap:palmed}, we
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introduced Palmed, whose main goal is to automatically produce port-mappings of
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CPUs without assuming the presence of specific hardware counters.
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\smallskip{}
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The ARM architectures occupy a growing space in the global computing ecosystem.
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They are already pervasive among the embedded and mobile devices, with most
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mobile phones featuring an ARM CPU~\cite{arm_mobile}. Processors based on ARM
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are emerging in datacenters and supercomputers: the Fugaku supercomputer
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---~considered the fastest supercomputer in the world by the TOP500
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ranking~\cite{fugaku_top500}~--- runs on ARM-based CPUs~\cite{fugaku_arm}, the
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MareNostrum 4 supercomputer has an ARM-based cluster~\cite{marenostrum4_arm}.
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Yet, the ARM ecosystem is still lacking in performance debugging tooling. While
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\llvmmca{} supports ARM, it is one of the only few: \iaca{}, made by Intel, is
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not supported ---~and will never be, as it is end-of-life~---; \uica{} is
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focused on Intel architectures, and cannot be easily ported as it heavily
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relies on reverse engineering specific to Intel, and enabled by specific
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hardware counters; Intel \texttt{VTune}, a commonly used profiling performance
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analysis tool, supports only x86-64.
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\smallskip{}
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In this context, modelling an ARM CPU ---~the Cortex A72~--- with Palmed seemed
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to be an important goal, especially meaningful as this particular CPU only has
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very few hardware counters. However, it yielded only mixed results, as shown in
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\autoref{sec:palmed_results}.
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In this chapter, we show that a major cause of imprecision in these results is
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the absence of a frontend model.
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\section{Necessity to go beyond ports}
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The resource models produced by \palmed{} are mainly concerned with the backend
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of the CPUs modeled. However, the importance of the frontend in the accuracy of
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a model's prediction cannot be ignored. Its effect can be clearly seen in the
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evaluation heatmaps of various code analyzers in \autoref{fig:palmed_heatmaps}.
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Each heatmap has a clear-cut limit on the horizontal axis: independently of the
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benchmark's content, it is impossible to reach more than a given number of
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instructions per cycle for a given processor ---~4 instructions for the
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\texttt{SKL-SP}, 5 for the \texttt{ZEN1}. This limit is imposed by the
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frontend.
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Some analyzers, such as \palmed{} and \iaca{}, model this limit: the heatmap
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shows that the predicted IPC will not surpass this limit. The other three
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analyzers studied, however, do not model this limit; for instance, \uopsinfo{}
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has a high density of benchmarks predicted at 8 instructions per cycle on
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SPEC2017 on the \texttt{SKL-SP} CPU, while the native measurement yielded only
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4 instructions per cycle. The same effect is visible on \pmevo{} and \llvmmca{}
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heatmaps.
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\begin{example}{High back-end throughput on \texttt{SKL-SP}}
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On the \texttt{SKL-SP} microarchitecture, assuming an infinitely large
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frontend, a number of instructions per cycle higher than 4 is easy to
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reach.
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According to \uopsinfo{} data, a 64-bits
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integer \lstxasm{addq} is processed with a single \uop{}, dispatched on
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port 0, 1, 5 or 6. In the meantime, a simple form 64 bits register store
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to a direct register-held address ---~\eg{} a \lstxasm{movq \%rax,
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(\%rbx)}~--- is also processed with a single \uop{}, dispatched on port 2
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or 3.
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Thus, backend-wise, the kernel $4\times \texttt{addq} + 2\times
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\texttt{mov}$ has a throughput of 6 instructions per cycle. However, in
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reality, this kernel would be frontend-bound, with a theoretical maximum throughput of 4
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instructions per cycle ---~in fact, a \pipedream{} measure only yields 3
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instructions per cycle.
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\end{example}
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\bigskip{}
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To account for this, \palmed{} tries to detect an additional resource, apart
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from the backend ports and combined ports, on which every \uop{} incurs a load.
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This allows \palmed{} to avoid large errors on frontend-bound kernels.
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The approach is, however, far from perfect. The clearest reason for this is is
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that the frontend, both on x86-64 and ARM architectures, works in-order, while
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\palmed{} inherently models kernels as multisets of instructions, thus
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completely ignoring ordering. This resource model is purely linear: an
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instruction incurs a load on the frontend resource in a fully commutative way,
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independently of the previous instructions executed this cycle and of many
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other effects.
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The article introducing \uica{}~\cite{uica} explores this question in detail
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for x86-64 Intel architectures. The authors, having previously developed
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\uopsinfo{}, discuss the importance of a correct modelling of the frontend to
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accurately predict throughput. Their approach, based on the exploration and
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reverse-engineering of the crucial parts of the frontend, showcases many
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important and non-trivial aspects of frontends usually neglected, such as the
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switching between the decoders and \uop{}-cache as source of instructions
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---~which cannot be linearly modelled.
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\section{The Cortex A72 CPU}
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The Cortex A72~\cite{a72_doc} is a CPU based on the ARMv8-A ISA ---~the first
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@ -8,6 +108,62 @@ high-performance core for low-power applications.
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The Raspberry Pi 4 uses a 4-cores A72 CPU, implemented by Broadcom as BCM2711;
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it is thus easy to have access to an A72 to run experiments.
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\paragraph{Backend.}
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\begin{figure}
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\centering
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\includegraphics[width=\linewidth]{A72_pipeline_diagram.svg}
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\caption{Simplified overview of the Cortex A72
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pipeline}\label{fig:a72_pipeline}
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\end{figure}
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\paragraph{Backend.} As can be seen in \autoref{fig:a72_pipeline} (adapted from
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the software optimization guide for the Cortex A72, published by
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ARM~\cite{ref:a72_optim}), the Cortex A72 has eight execution ports:
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\begin{itemize}
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\item a branch port (branch instructions, equivalent to x86 jumps);
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\item two identical integer ports (integer arithmetic operation);
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\item an integer multi-cycle port (complex integer operations, \eg{} divisions);
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\item two nearly-identical floating point and SIMD ports (mostly identical,
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with slight specializations: \eg{} only port FP0 can do SIMD
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multiplication, while only port FP1 can do floating point comparisons);
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\item a load port;
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\item a store port.
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\end{itemize}
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\paragraph{Frontend.} The Cortex A72 frontend can only decode three
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instructions and dispatch three \uops{} per cycle~\cite{ref:a72_optim}.
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Intel's \texttt{SKL-SP}, which we considered before, has a frontend that
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bottlenecks at four \uops{} per cycle~\cite{agnerfog_skl_front4}. This
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difference of one \uop{} per cycle is actually meaningful, as this means that
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only three of the eight backend ports can be used each cycle.
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\begin{example}[2nd order polynomial evaluation]
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Consider a kernel evaluating the 2nd order polynomial expression for
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different values of $x$:
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\begin{align*}
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P[i] &= a{X[i]}^2 + bX[i] + c \\
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&= \left( aX[i] + b \right) \times X[i] + c
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\end{align*}
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which directly translates to four operations: load $X[i]$, two floating
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point multiply-add, store the result $P[i]$. The backend, having a load
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port, two SIMD ports and a store port, can execute one iteration of such a
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kernel every cycle; in steady-state, out-of-order execution can lift the
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latency-induced pressure. However, as the frontend bottlenecks at three \uops{}
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per cycle, this kernel does not fit in a single cycle.
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\end{example}
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\paragraph{Lack of hardware counters.}
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The Cortex A72 only features a very limited set of specialized hardware counters.
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While the CPU is able to report the number of elapsed cycles,
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retired instructions, branch misses and various metrics on cache misses, it
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does not report any event regarding macro- or micro-operations, dispatching or
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issuing to specific ports. This makes it, as pointed before, a particularly
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relevant target for \palmed{}.
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\section{Manually modelling the A72 frontend}
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% TODO
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\subsection{Methodology}
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\cite{ref:a72_optim}
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Before Width: | Height: | Size: 24 KiB After Width: | Height: | Size: 25 KiB |
|
|
@ -107,6 +107,14 @@
|
|||
doi={10.1109/PMBS49563.2019.00006}
|
||||
}
|
||||
|
||||
@online{AgnerFog,
|
||||
author = {Agner Fog},
|
||||
title = {Instruction tables: Lists of instruction latencies, through-puts and micro-operation breakdowns for Intel, {AMD} and {VIA} {CPU}s},
|
||||
publisher = {Technical University of Denmark},
|
||||
year = {2020},
|
||||
url = {http://www.agner.org/optimize/instruction_tables.pdf},
|
||||
}
|
||||
|
||||
@inproceedings{uopsinfo,
|
||||
title = {uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures},
|
||||
acmid = {3304062},
|
||||
|
|
|
|||
|
|
@ -90,3 +90,46 @@
|
|||
year = {2015},
|
||||
month = {March},
|
||||
}
|
||||
|
||||
@misc{agnerfog_skl_front4,
|
||||
title={Discussion on blogpost},
|
||||
author={Fog, Agner},
|
||||
year=2016,
|
||||
howpublished={\url{https://www.agner.org/optimize/blog/read.php?i=581}}
|
||||
}
|
||||
|
||||
@INPROCEEDINGS{fugaku_arm,
|
||||
author={Matsuoka, Satoshi},
|
||||
booktitle={2021 Symposium on VLSI Circuits},
|
||||
title={Fugaku and A64FX: the First Exascale Supercomputer and its Innovative Arm CPU},
|
||||
year={2021},
|
||||
volume={},
|
||||
number={},
|
||||
pages={1-3},
|
||||
doi={10.23919/VLSICircuits52068.2021.9492415}
|
||||
}
|
||||
|
||||
@misc{fugaku_top500,
|
||||
title={Supercomputer Fugaku retains first place worldwide in HPCG and Graph500 rankings},
|
||||
year=2022,
|
||||
month=November,
|
||||
author={{Fujitsu Limited}},
|
||||
howpublished={\url{https://www.fujitsu.com/global/about/resources/news/press-releases/2022/1115-01.html}}
|
||||
}
|
||||
|
||||
@misc{marenostrum4_arm,
|
||||
title={Technical information on the MareNostrum 4 supercomputer's ARM cluster},
|
||||
author={{Barcelona Supercomputing Center}},
|
||||
year=2020,
|
||||
howpublished={\url{https://www.bsc.es/innovation-and-services/technical-information-cte-arm}}
|
||||
}
|
||||
|
||||
@misc{arm_mobile,
|
||||
title={Together, we are building the future of computing, on Arm},
|
||||
author={Rene Haas},
|
||||
organization = {ARM},
|
||||
year=2023,
|
||||
month=September,
|
||||
howpublished={\url{https://www.arm.com/company/news/2023/09/building-the-future-of-computing-on-arm}},
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,10 +12,19 @@
|
|||
* Notion of bottleneck
|
||||
[[END]]
|
||||
|
||||
* Palmed was made to produce models for architectures with limited hardware
|
||||
counters
|
||||
* ARM is an important architecture:
|
||||
* already pervasive in embedded devices
|
||||
* starts to emerge in the datacenter [Fugaku, MareNostrum 4]
|
||||
* …and lacks HW counters
|
||||
* Cf prev. chapter: Palmed results on the Cortex A72 are not that good. Why?
|
||||
|
||||
## Necessity to go beyond ports
|
||||
|
||||
* Palmed: concerned mostly with ports
|
||||
* Noticed the importance of the frontend while investigating its performances
|
||||
on x86
|
||||
* heatmap representation: uops predicts unreachably high IPCs (eg. 8 on SKX)
|
||||
* example of a frontend-bound microkernel
|
||||
* Palmed's vision of a frontend
|
||||
|
|
@ -50,8 +59,6 @@
|
|||
* Very few hardware counters regarding the frontend! In particular, no access
|
||||
*at all* to macro-ops. No micro-op count.
|
||||
|
||||
* Pure Palmed results
|
||||
|
||||
## Manual frontend
|
||||
|
||||
### Base methodology
|
||||
|
|
|
|||
Loading…
Reference in a new issue