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A72: nocross model: start writeup

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Théophile Bastian 2023-09-21 17:48:47 +02:00
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manuscrit/40_A72-frontend/30_manual_frontend.tex
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@ -180,3 +180,47 @@ model mapping each supported instruction of the ISA to its \uop{} count.
which is consistent. We conclude that $\mucount i = 3\cyc{\kerK_3} = 4-2 =
2$.
\end{example}
\subsection{Bubbles in the pipeline}
The frontend, however, does not always exhibit a purely linear behaviour. We
consider for instance the kernel $\kerK =$ \lstarmasm{ADDV_FD_H_VN_V_8H} $+
3\times\basic{Int01}$; for the rest of this chapter, we refer to
\lstarmasm{ADDV_FD_H_VN_V_8H} as simply \lstarmasm{ADDV} when not stated
otherwise.
Backend-wise, \texttt{ADDV} fully loads \texttt{FP1} and \texttt{FP01}, while
$\basic{Int01}$ half-loads \texttt{Int01}. The port most loaded by $\kerK$ is
thus \texttt{Int01}, with a load of $1\,\sfrac{1}{2}$. We then expect
$\cycB{\kerK} = 1\,\sfrac{1}{2}$.
Frontend-wise, \texttt{ADDV} decomposes into two \uops{}, while $\basic{Int01}$
decomposes into a single \uops{}; thus, $\mucount{}\kerK = 5$. We then expect
$\cycF{\kerK} = 1\,\sfrac{2}{3}$.
As the frontend dominates the backend, we expect $\cyc{\kerK} = \cycF{\kerK} =
1\,\sfrac{2}{3}$. However, in reality, we measure $\cyc{\kerK} = 2.01 \simeq 2$
cycles.
\medskip{}
From then on, we strive to find a model that could reliably predict, given a
kernel, how many cycles it requires to execute, frontend-wise, in a
steady-state.
\subsubsection{No-cross model}
\begin{figure}
\centering
\includegraphics[width=0.7\linewidth]{timeline_front_nocross.svg}
\end{figure}
On the x86-64 architectures they analyzed, \uica{}'s authors find that the
CPU's predecoder might cause an instruction's \uops{} to be postponed to the
next cycle if it is pre-decoded across a cycle boundary~\cite{uica} (§4.1).
We hypothesize that the same kind of effect could postpone an instruction's
\uops{} until the next cycle if its \uops{} would cross a cycle boundary
otherwise, as illustrated in \qtodo{ref}.

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