Minor fixes
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3 changed files with 9 additions and 5 deletions
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@ -37,7 +37,9 @@ physical registers than what is exposed to the user through the ISA; a renaming
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phrase will allocate those registers to avoid the effects of WaR and WaW
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dependencies as much as possible.
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\smallskip{} For the present chapter, \textit{we only consider read-after-write
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\smallskip{}
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For the present chapter, \textit{we only consider read-after-write
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dependencies}; however, all the techniques we present are applicable to other
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types of dependencies if the considered architecture requires to take them into
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account.
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@ -11,7 +11,7 @@ detected by keeping track of which instruction last wrote each register in a
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Loop-carried dependencies can, to some extent, be detected the same way. As the
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basic block is always assumed to be the body of an infinite loop, a
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straight-line analysis can be performed on a duplicated kernel. This strategy
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is \eg{} adopted by \osaca{}~\cite{osaca2} (§II.D). When dealing only with
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is \eg{} adopted by \osaca{}~\cite[§II.D]{osaca2}. When dealing only with
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register accesses, this strategy is always sufficient: as each iteration always
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executes the same basic block, it is not possible for an instruction to depend
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on another instruction two iterations earlier or more.
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@ -20,10 +20,11 @@ performance}\label{ssec:staticdeps:rob_proof}
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instructions $\left(I_{p+kn}, I_{q+kn}\right)_{k\in\nat}$.
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\end{theorem}
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To prove this assertion, we require a few postulates describing the functioning
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of a CPU and, in particular, how \uops{} transit in (decoded) and out (retired)
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the reorder buffer.
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To prove this assertion, we require a few postulates to model the functioning
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of a CPU and, in particular, how \uops{} transit in (decoded) and out
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(retired) the reorder buffer.
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\needspace{10em}
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\begin{postulate}[Reorder buffer as a circular buffer]
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The reorder buffer is a circular buffer of size $R \in \nat^+$.
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It contains only decoded \uops{}.
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@ -90,6 +91,7 @@ Consequently, if both $i_q$ and $i_{q'}$ are in-flight then
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$|q'-q|<R$, and thus $\distance{I_p}{I_{p'}} < R - 1$.
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\end{proof}
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\needspace{15em}
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\begin{postulate}[Issue delay]
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Reasons why the issue of a \uop{} $i$ is delayed can be:
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\begin{enumerate}
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