128 lines
4.4 KiB
TeX
128 lines
4.4 KiB
TeX
\section{Foundations}
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\begin{frame}{Bird's eye view of a CPU}
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\centering
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\includegraphics[height=0.94\textheight]{cpu_big_picture.svg}
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\end{frame}
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\begin{frame}{Possible bottlenecks}
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\begin{columns}
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\begin{column}{0.37\textwidth}
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\begin{center}
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\includegraphics[width=\textwidth]{cpu_big_picture_truncate.svg}
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\end{center}
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\end{column}
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\hfill
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\begin{column}{0.62\textwidth}
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\begin{tightitemize}{0pt}
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\begin{itemize}
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\item \alert{Frontend:} \uops{} not issued fast enough
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\bigskip
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\item \alert{Backend:} saturated execution units
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\bigskip
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\item \alert{Dependencies:} computation is stalled waiting
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for previous results
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\end{itemize}
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\end{tightitemize}
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\end{column}
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\end{columns}
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\end{frame}
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%\begin{frame}{Dependencies and the ROB}
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% \begin{columns}
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% \begin{column}{0.35\textwidth}
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% \begin{center}
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% \includegraphics[width=\textwidth]{cpu_frontend.svg}
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% \end{center}
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% \end{column}
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% \hfill
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% \begin{column}{0.64\textwidth}
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% \begin{tightitemize}{0pt}
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% \begin{itemize}
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% \item Dependencies can stall execution
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% \item Maybe instructions further down can be executed right now?
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% \end{itemize}
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% \begin{center}
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% \textbf{\alert{$\to$ Out-of-Order CPUs}}
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% \end{center}
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% \begin{itemize}
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% \item ROB: circular buffer of \uops{}
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% \item First possible instruction is issued
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% \end{itemize}
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% \end{tightitemize}
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% \end{column}
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% \end{columns}
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%\end{frame}
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%\begin{frame}{How do we get insights from this complex system?}
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% \textbf{Hardware counters}
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% \begin{itemize}
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% \item Built-in hardware, counters gathered at runtime
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% \item Very accurate
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% \item Available data varies from model to model
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% \item May not even be available at all
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% \end{itemize}
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%
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% \textbf{Simulation?}
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% \begin{itemize}
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% \item A modern CPU is \alert{$\sim$\,100e9 transistors}: very complex
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% models!
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% \item Very expensive, even for manufacturers for design validation
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% \item CPU design is industrial secret $\leadsto$ not available anyway
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% \item \ldots{}\ie{} not feasible.
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% \end{itemize}
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%\end{frame}
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\begin{frame}{Code analyzers}
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\begin{itemize}
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\item That predict performance of a piece of assembly
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\item Features microarchitectural models
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\item Most often static analyzers
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\item Predict at least the \emph{reverse-throughput} $\cyc{\kerK}$ of a
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kernel $\kerK$ (cycles per iteration)
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\item May derive further useful metrics, \eg{} bottlenecks, by
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inspecting their model at will
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\end{itemize}
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\end{frame}
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\begin{frame}{What can be analyzed?}
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Pieces of code referred as \alert{``microkernels''}:
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\begin{itemize}
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\item body of an (assumed) infinite loop;
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\item in steady-state;
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\item straight-line code (branches assumed not taken);
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\item L1-resident (memory model is out of scope).
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\end{itemize}
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Reasonable hypotheses for the category of codes worth optimizing this way!
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\end{frame}
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\begin{frame}{Existing code analyzers}
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\begin{itemize}
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\item Intel \alert{\iaca{}}: proprietary, Intel CPUs only. First
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``good'' code analyzer, now deprecated. Was (is?) widely used.
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\item \alert{\llvmmca{}}: FOSS, production-grade, many
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microarchitectures. Based on data from the \texttt{llvm} compiler.
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\item \alert{\uica{}} and \alert{\uopsinfo{}}: research, good accuracy.
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Intel CPUs.
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\item \alert{\ithemal{}}: machine-learning based.
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\end{itemize}
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\bigskip
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Except Ithemal, \alert{all} are (to some extent) based on manually-made
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models!\\
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\pause{}
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\bigskip{}
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\begin{center}
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\textbf{\alert{Ambition:}} \alert{automated} model generation.
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\end{center}
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\end{frame}
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\begin{frame}{When I started my PhD\ldots}
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\centering
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%\includegraphics[height=0.9\textheight]{patate_placeholder.jpg}
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\includegraphics[height=0.9\textheight]{sota_potato.svg}
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\end{frame}
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