16c00db4bb
Pull AFS fixes from David Howells:
"Here's a set of patches that fix a number of bugs in the in-kernel AFS
client, including:
- Fix directory locking to not use individual page locks for
directory reading/scanning but rather to use a semaphore on the
afs_vnode struct as the directory contents must be read in a single
blob and data from different reads must not be mixed as the entire
contents may be shuffled about between reads.
- Fix address list parsing to handle port specifiers correctly.
- Only give up callback records on a server if we actually talked to
that server (we might not be able to access a server).
- Fix some callback handling bugs, including refcounting,
whole-volume callbacks and when callbacks actually get broken in
response to a CB.CallBack op.
- Fix some server/address rotation bugs, including giving up if we
can't probe a server; giving up if a server says it doesn't have a
volume, but there are more servers to try.
- Fix the decoding of fetched statuses to be OpenAFS compatible.
- Fix the handling of server lookups in Cache Manager ops (such as
CB.InitCallBackState3) to use a UUID if possible and to handle no
server being found.
- Fix a bug in server lookup where not all addresses are compared.
- Fix the non-encryption of calls that prevents some servers from
being accessed (this also requires an AF_RXRPC patch that has
already gone in through the net tree).
There's also a patch that adds tracepoints to log Cache Manager ops
that don't find a matching server, either by UUID or by address"
* tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs:
afs: Fix the non-encryption of calls
afs: Fix CB.CallBack handling
afs: Fix whole-volume callback handling
afs: Fix afs_find_server search loop
afs: Fix the handling of an unfound server in CM operations
afs: Add a tracepoint to record callbacks from unlisted servers
afs: Fix the handling of CB.InitCallBackState3 to find the server by UUID
afs: Fix VNOVOL handling in address rotation
afs: Fix AFSFetchStatus decoder to provide OpenAFS compatibility
afs: Fix server rotation's handling of fileserver probe failure
afs: Fix refcounting in callback registration
afs: Fix giving up callbacks on server destruction
afs: Fix address list parsing
afs: Fix directory page locking
173 lines
8.6 KiB
JSON
173 lines
8.6 KiB
JSON
[
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{
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"BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "LLC_MISSES.MEM_READ",
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"PerPkg": "1",
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"ScaleUnit": "64Bytes",
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"UMask": "0x3",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "LLC_MISSES.MEM_WRITE",
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"PerPkg": "1",
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"ScaleUnit": "64Bytes",
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"UMask": "0xC",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Memory controller clock ticks",
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"Counter": "0,1,2,3",
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"EventName": "UNC_M_CLOCKTICKS",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
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"Counter": "0,1,2,3",
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"EventCode": "0x85",
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"EventName": "UNC_M_POWER_CHANNEL_PPD",
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"MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
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"MetricName": "power_channel_ppd %",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Cycles Memory is in self refresh power mode",
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"Counter": "0,1,2,3",
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"EventCode": "0x43",
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"EventName": "UNC_M_POWER_SELF_REFRESH",
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"MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
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"MetricName": "power_self_refresh %",
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"PerPkg": "1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Pre-charges due to page misses",
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"Counter": "0,1,2,3",
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"EventCode": "0x2",
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"EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
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"PerPkg": "1",
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"UMask": "0x1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Pre-charge for reads",
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"Counter": "0,1,2,3",
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"EventCode": "0x2",
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"EventName": "UNC_M_PRE_COUNT.RD",
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"PerPkg": "1",
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"UMask": "0x4",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Pre-charge for writes",
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"Counter": "0,1,2,3",
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"EventCode": "0x2",
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"EventName": "UNC_M_PRE_COUNT.WR",
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"PerPkg": "1",
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"UMask": "0x8",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "DRAM Page Activate commands sent due to a write request",
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"Counter": "0,1,2,3",
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"EventCode": "0x1",
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"EventName": "UNC_M_ACT_COUNT.WR",
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"PerPkg": "1",
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"PublicDescription": "Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller). Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.",
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"UMask": "0x2",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "All DRAM CAS Commands issued",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "UNC_M_CAS_COUNT.ALL",
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"PerPkg": "1",
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"PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
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"UMask": "0xF",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "LLC_MISSES.MEM_READ",
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"PerPkg": "1",
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"ScaleUnit": "64Bytes",
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"UMask": "0x3",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills) ",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "UNC_M_CAS_COUNT.RD_REG",
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"PerPkg": "1",
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"PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read. This event only counts regular reads and does not includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
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"UMask": "0x1",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "DRAM Underfill Read CAS Commands issued",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
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"PerPkg": "1",
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"PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads. Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request). ",
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"UMask": "0x2",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "LLC_MISSES.MEM_WRITE",
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"PerPkg": "1",
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"ScaleUnit": "64Bytes",
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"UMask": "0xC",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Read Pending Queue Allocations",
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"Counter": "0,1,2,3",
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"EventCode": "0x10",
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"EventName": "UNC_M_RPQ_INSERTS",
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"PerPkg": "1",
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"PublicDescription": "Counts the number of read requests allocated into the Read Pending Queue (RPQ). This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. The requests deallocate after the read CAS command has been issued to DRAM. This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ. ",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Read Pending Queue Occupancy",
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"Counter": "0,1,2,3",
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"EventCode": "0x80",
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"EventName": "UNC_M_RPQ_OCCUPANCY",
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"PerPkg": "1",
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"PublicDescription": "Counts the number of entries in the Read Pending Queue (RPQ) at each cycle. This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory.",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Write Pending Queue Allocations",
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"Counter": "0,1,2,3",
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"EventCode": "0x20",
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"EventName": "UNC_M_WPQ_INSERTS",
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"PerPkg": "1",
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"PublicDescription": "Counts the number of writes requests allocated into the Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller). The write requests deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "Write Pending Queue Occupancy",
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"Counter": "0,1,2,3",
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"EventCode": "0x81",
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"EventName": "UNC_M_WPQ_OCCUPANCY",
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"PerPkg": "1",
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"PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests.",
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"Unit": "iMC"
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}
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]
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