m2-internship/perf-eh_elf
1
0
Fork 0
Code Issues 1 Pull requests Releases Wiki Activity
perf-eh_elf/pmu-events/arch/x86/silvermont/cache.json
Linus Torvalds 16c00db4bb Merge tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs 
Pull AFS fixes from David Howells:
 "Here's a set of patches that fix a number of bugs in the in-kernel AFS
  client, including:

   - Fix directory locking to not use individual page locks for
     directory reading/scanning but rather to use a semaphore on the
     afs_vnode struct as the directory contents must be read in a single
     blob and data from different reads must not be mixed as the entire
     contents may be shuffled about between reads.

   - Fix address list parsing to handle port specifiers correctly.

   - Only give up callback records on a server if we actually talked to
     that server (we might not be able to access a server).

   - Fix some callback handling bugs, including refcounting,
     whole-volume callbacks and when callbacks actually get broken in
     response to a CB.CallBack op.

   - Fix some server/address rotation bugs, including giving up if we
     can't probe a server; giving up if a server says it doesn't have a
     volume, but there are more servers to try.

   - Fix the decoding of fetched statuses to be OpenAFS compatible.

   - Fix the handling of server lookups in Cache Manager ops (such as
     CB.InitCallBackState3) to use a UUID if possible and to handle no
     server being found.

   - Fix a bug in server lookup where not all addresses are compared.

   - Fix the non-encryption of calls that prevents some servers from
     being accessed (this also requires an AF_RXRPC patch that has
     already gone in through the net tree).

  There's also a patch that adds tracepoints to log Cache Manager ops
  that don't find a matching server, either by UUID or by address"

* tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs:
  afs: Fix the non-encryption of calls
  afs: Fix CB.CallBack handling
  afs: Fix whole-volume callback handling
  afs: Fix afs_find_server search loop
  afs: Fix the handling of an unfound server in CM operations
  afs: Add a tracepoint to record callbacks from unlisted servers
  afs: Fix the handling of CB.InitCallBackState3 to find the server by UUID
  afs: Fix VNOVOL handling in address rotation
  afs: Fix AFSFetchStatus decoder to provide OpenAFS compatibility
  afs: Fix server rotation's handling of fileserver probe failure
  afs: Fix refcounting in callback registration
  afs: Fix giving up callbacks on server destruction
  afs: Fix address list parsing
  afs: Fix directory page locking
2018-05-15 10:48:36 -07:00

812 lines
No EOL
32 KiB
JSON
Raw Blame History

[
{
"PublicDescription": "This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims).",
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "L2_REJECT_XQ.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ"
},
{
"PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.)",
"EventCode": "0x31",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "CORE_REJECT_L2Q.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL."
},
{
"PublicDescription": "This event counts requests originating from the core that references a cache line in the L2 cache.",
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"SampleAfterValue": "200003",
"BriefDescription": "L2 cache requests from this core"
},
{
"PublicDescription": "This event counts the total number of L2 cache references and the number of L2 cache misses respectively.",
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "LONGEST_LAT_CACHE.MISS",
"SampleAfterValue": "200003",
"BriefDescription": "L2 cache request misses"
},
{
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.\r\nCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events. \r\n",
"EventCode": "0x86",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss."
},
{
"PEBS": "1",
"PublicDescription": "This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch.",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "REHABQ.LD_BLOCK_ST_FORWARD",
"SampleAfterValue": "200003",
"BriefDescription": "Loads blocked due to store forward restriction"
},
{
"PublicDescription": "This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time.",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "REHABQ.LD_BLOCK_STD_NOTREADY",
"SampleAfterValue": "200003",
"BriefDescription": "Loads blocked due to store data not ready"
},
{
"PublicDescription": "This event counts the number of retire stores that experienced cache line boundary splits.",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "REHABQ.ST_SPLITS",
"SampleAfterValue": "200003",
"BriefDescription": "Store uops that split cache line boundary"
},
{
"PEBS": "1",
"PublicDescription": "This event counts the number of retire loads that experienced cache line boundary splits.",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "REHABQ.LD_SPLITS",
"SampleAfterValue": "200003",
"BriefDescription": "Load uops that split cache line boundary"
},
{
"PublicDescription": "This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0).",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "REHABQ.LOCK",
"SampleAfterValue": "200003",
"BriefDescription": "Uops with lock semantics"
},
{
"PublicDescription": "This event counts the number of retired stores that are delayed because there is not a store address buffer available.",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "REHABQ.STA_FULL",
"SampleAfterValue": "200003",
"BriefDescription": "Store address buffer full"
},
{
"PublicDescription": "This event counts the number of load uops reissued from Rehabq.",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "REHABQ.ANY_LD",
"SampleAfterValue": "200003",
"BriefDescription": "Any reissued load uops"
},
{
"PublicDescription": "This event counts the number of store uops reissued from Rehabq.",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x80",
"EventName": "REHABQ.ANY_ST",
"SampleAfterValue": "200003",
"BriefDescription": "Any reissued store uops"
},
{
"PublicDescription": "This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.",
"EventCode": "0x04",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS",
"SampleAfterValue": "200003",
"BriefDescription": "Loads missed L1"
},
{
"PEBS": "1",
"PublicDescription": "This event counts the number of load ops retired that hit in the L2.",
"EventCode": "0x04",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS",
"SampleAfterValue": "200003",
"BriefDescription": "Loads hit L2"
},
{
"PEBS": "1",
"PublicDescription": "This event counts the number of load ops retired that miss in the L2.",
"EventCode": "0x04",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS",
"SampleAfterValue": "100007",
"BriefDescription": "Loads missed L2"
},
{
"PublicDescription": "This event counts the number of load ops retired that had UTLB miss.",
"EventCode": "0x04",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "MEM_UOPS_RETIRED.UTLB_MISS",
"SampleAfterValue": "200003",
"BriefDescription": "Loads missed UTLB"
},
{
"PEBS": "1",
"PublicDescription": "This event counts the number of load ops retired that got data from the other core or from the other module.",
"EventCode": "0x04",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "MEM_UOPS_RETIRED.HITM",
"SampleAfterValue": "200003",
"BriefDescription": "Cross core or cross module hitm"
},
{
"PublicDescription": "This event counts the number of load ops retired.",
"EventCode": "0x04",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"SampleAfterValue": "200003",
"BriefDescription": "All Loads"
},
{
"PublicDescription": "This event counts the number of store ops retired.",
"EventCode": "0x04",
"Counter": "0,1",
"UMask": "0x80",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"SampleAfterValue": "200003",
"BriefDescription": "All Stores"
},
{
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"EventCode": "0xB7",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100007",
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680000044",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any code reads (demand & prefetch) that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1000000044",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0400000044",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0200000044",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0000010044",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any code reads (demand & prefetch) that have any response type.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680000022",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1000000022",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0400000022",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0200000022",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0000010022",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any rfo reads (demand & prefetch) that have any response type.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680003091",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any data read (demand & prefetch) that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1000003091",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0400003091",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0200003091",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any data read (demand & prefetch) that miss L2 with a snoop miss response.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0000013091",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any data read (demand & prefetch) that have any response type.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680004800",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts streaming store that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1000008008",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any request that hit in the other module where modified copies were found in other core's L1 cache.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0400008008",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0200008008",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any request that miss L2 with a snoop miss response.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0000018008",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any request that have any response type.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680002000",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts DCU hardware prefetcher data read that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1000002000",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0400002000",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0200002000",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0000012000",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts DCU hardware prefetcher data read that have any response type.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680000100",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Countsof demand RFO requests to write to partial cache lines that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680000080",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand reads of partial cache lines (including UC and WC) that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680000040",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0400000040",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0200000040",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680000020",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1000000020",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0400000020",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0200000020",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680000010",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1000000010",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0400000010",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0200000010",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680000008",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts writeback (modified to exclusive) that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080000008",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x4000000004",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680000004",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0400000004",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0200000004",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0000010004",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that have any response type.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x4000000002",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680000002",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1000000002",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0400000002",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0200000002",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x4000000001",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1680000001",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch data read that miss L2.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x1000000001",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0400000001",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0200000001",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch data read that miss L2 with a snoop miss response.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0000010001",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand and DCU prefetch data read that have any response type.",
"Offcore": "1"
}
]
Reference in a new issue View git blame Copy permalink