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perf-eh_elf/pmu-events/arch/x86/knightslanding/pipeline.json
Linus Torvalds 16c00db4bb Merge tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs 
Pull AFS fixes from David Howells:
 "Here's a set of patches that fix a number of bugs in the in-kernel AFS
  client, including:

   - Fix directory locking to not use individual page locks for
     directory reading/scanning but rather to use a semaphore on the
     afs_vnode struct as the directory contents must be read in a single
     blob and data from different reads must not be mixed as the entire
     contents may be shuffled about between reads.

   - Fix address list parsing to handle port specifiers correctly.

   - Only give up callback records on a server if we actually talked to
     that server (we might not be able to access a server).

   - Fix some callback handling bugs, including refcounting,
     whole-volume callbacks and when callbacks actually get broken in
     response to a CB.CallBack op.

   - Fix some server/address rotation bugs, including giving up if we
     can't probe a server; giving up if a server says it doesn't have a
     volume, but there are more servers to try.

   - Fix the decoding of fetched statuses to be OpenAFS compatible.

   - Fix the handling of server lookups in Cache Manager ops (such as
     CB.InitCallBackState3) to use a UUID if possible and to handle no
     server being found.

   - Fix a bug in server lookup where not all addresses are compared.

   - Fix the non-encryption of calls that prevents some servers from
     being accessed (this also requires an AF_RXRPC patch that has
     already gone in through the net tree).

  There's also a patch that adds tracepoints to log Cache Manager ops
  that don't find a matching server, either by UUID or by address"

* tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs:
  afs: Fix the non-encryption of calls
  afs: Fix CB.CallBack handling
  afs: Fix whole-volume callback handling
  afs: Fix afs_find_server search loop
  afs: Fix the handling of an unfound server in CM operations
  afs: Add a tracepoint to record callbacks from unlisted servers
  afs: Fix the handling of CB.InitCallBackState3 to find the server by UUID
  afs: Fix VNOVOL handling in address rotation
  afs: Fix AFSFetchStatus decoder to provide OpenAFS compatibility
  afs: Fix server rotation's handling of fileserver probe failure
  afs: Fix refcounting in callback registration
  afs: Fix giving up callbacks on server destruction
  afs: Fix address list parsing
  afs: Fix directory page locking
2018-05-15 10:48:36 -07:00

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[
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of branch instructions retired"
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0x7e",
"EventName": "BR_INST_RETIRED.JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xfe",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps and predicted taken."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xf9",
"EventName": "BR_INST_RETIRED.CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of near CALL branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xfd",
"EventName": "BR_INST_RETIRED.REL_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of near relative CALL branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xfb",
"EventName": "BR_INST_RETIRED.IND_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of near indirect CALL branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xf7",
"EventName": "BR_INST_RETIRED.RETURN",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of near RET branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xeb",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xbf",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of far branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted branch instructions retired"
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0x7e",
"EventName": "BR_MISP_RETIRED.JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xfe",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xfb",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xf7",
"EventName": "BR_MISP_RETIRED.RETURN",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xeb",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP."
},
{
"PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.",
"EventCode": "0xC2",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "UOPS_RETIRED.MS",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS)."
},
{
"PublicDescription": "This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. ",
"EventCode": "0xC2",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "UOPS_RETIRED.ALL",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of micro-ops retired"
},
{
"PublicDescription": "This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt.",
"EventCode": "0xC2",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "UOPS_RETIRED.SCALAR_SIMD",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt."
},
{
"PublicDescription": "This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
"EventCode": "0xC2",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "UOPS_RETIRED.PACKED_SIMD",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies."
},
{
"EventCode": "0xC3",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page"
},
{
"PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.",
"EventCode": "0xC3",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of floating operations retired that required microcode assists"
},
{
"EventCode": "0xC3",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "MACHINE_CLEARS.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all nukes"
},
{
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "NO_ALLOC_CYCLES.ROB_FULL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the ROB is full"
},
{
"PublicDescription": "This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.",
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "NO_ALLOC_CYCLES.MISPREDICTS",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire."
},
{
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "NO_ALLOC_CYCLES.RAT_STALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted. "
},
{
"PublicDescription": "This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched.",
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x90",
"EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation."
},
{
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x7f",
"EventName": "NO_ALLOC_CYCLES.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the total number of core cycles when no micro-ops are allocated for any reason."
},
{
"EventCode": "0xCB",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "RS_FULL_STALL.MEC",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry."
},
{
"EventCode": "0xCB",
"Counter": "0,1",
"UMask": "0x1f",
"EventName": "RS_FULL_STALL.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full. "
},
{
"EventCode": "0xC0",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the total number of instructions retired"
},
{
"PublicDescription": "This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides.",
"EventCode": "0xCD",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "CYCLES_DIV_BUSY.ALL",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider. "
},
{
"PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.",
"EventCode": "0x00",
"Counter": "Fixed counter 1",
"UMask": "0x1",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Fixed Counter: Counts the number of instructions retired"
},
{
"EventCode": "0x3C",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of unhalted core clock cycles"
},
{
"EventCode": "0x3C",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of unhalted reference clock cycles"
},
{
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter\r\n",
"EventCode": "0x00",
"Counter": "Fixed counter 2",
"UMask": "0x2",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles"
},
{
"EventCode": "0x00",
"Counter": "Fixed counter 3",
"UMask": "0x3",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles"
},
{
"EventCode": "0xE6",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "BACLEARS.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end."
},
{
"EventCode": "0xE6",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "BACLEARS.RETURN",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end."
},
{
"EventCode": "0xE6",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "BACLEARS.COND",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end."
},
{
"PEBS": "1",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store ",
"Data_LA": "1"
},
{
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "RECYCLEQ.LD_BLOCK_STD_NOTREADY",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready"
},
{
"PublicDescription": "This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once.",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "RECYCLEQ.ST_SPLITS",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once."
},
{
"PEBS": "1",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "RECYCLEQ.LD_SPLITS",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once.",
"Data_LA": "1"
},
{
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "RECYCLEQ.LOCK",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all the retired locked loads. It does not include stores because we would double count if we count stores"
},
{
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "RECYCLEQ.STA_FULL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full"
},
{
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "RECYCLEQ.ANY_LD",
"SampleAfterValue": "200003",
"BriefDescription": "Counts any retired load that was pushed into the recycle queue for any reason."
},
{
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x80",
"EventName": "RECYCLEQ.ANY_ST",
"SampleAfterValue": "200003",
"BriefDescription": "Counts any retired store that was pushed into the recycle queue for any reason."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xf9",
"EventName": "BR_MISP_RETIRED.CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted near CALL branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xfd",
"EventName": "BR_MISP_RETIRED.REL_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted near relative CALL branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xbf",
"EventName": "BR_MISP_RETIRED.FAR_BRANCH",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted far branch instructions retired."
}
]
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