16c00db4bb
Pull AFS fixes from David Howells:
"Here's a set of patches that fix a number of bugs in the in-kernel AFS
client, including:
- Fix directory locking to not use individual page locks for
directory reading/scanning but rather to use a semaphore on the
afs_vnode struct as the directory contents must be read in a single
blob and data from different reads must not be mixed as the entire
contents may be shuffled about between reads.
- Fix address list parsing to handle port specifiers correctly.
- Only give up callback records on a server if we actually talked to
that server (we might not be able to access a server).
- Fix some callback handling bugs, including refcounting,
whole-volume callbacks and when callbacks actually get broken in
response to a CB.CallBack op.
- Fix some server/address rotation bugs, including giving up if we
can't probe a server; giving up if a server says it doesn't have a
volume, but there are more servers to try.
- Fix the decoding of fetched statuses to be OpenAFS compatible.
- Fix the handling of server lookups in Cache Manager ops (such as
CB.InitCallBackState3) to use a UUID if possible and to handle no
server being found.
- Fix a bug in server lookup where not all addresses are compared.
- Fix the non-encryption of calls that prevents some servers from
being accessed (this also requires an AF_RXRPC patch that has
already gone in through the net tree).
There's also a patch that adds tracepoints to log Cache Manager ops
that don't find a matching server, either by UUID or by address"
* tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs:
afs: Fix the non-encryption of calls
afs: Fix CB.CallBack handling
afs: Fix whole-volume callback handling
afs: Fix afs_find_server search loop
afs: Fix the handling of an unfound server in CM operations
afs: Add a tracepoint to record callbacks from unlisted servers
afs: Fix the handling of CB.InitCallBackState3 to find the server by UUID
afs: Fix VNOVOL handling in address rotation
afs: Fix AFSFetchStatus decoder to provide OpenAFS compatibility
afs: Fix server rotation's handling of fileserver probe failure
afs: Fix refcounting in callback registration
afs: Fix giving up callbacks on server destruction
afs: Fix address list parsing
afs: Fix directory page locking
305 lines
No EOL
13 KiB
JSON
305 lines
No EOL
13 KiB
JSON
[
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{
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"PublicDescription": "Counts cycles the IDQ is empty.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x2",
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"EventName": "IDQ.EMPTY",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x4",
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"EventName": "IDQ.MITE_UOPS",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x4",
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"EventName": "IDQ.MITE_CYCLES",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x8",
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"EventName": "IDQ.DSB_UOPS",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x8",
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"EventName": "IDQ.DSB_CYCLES",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x10",
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"EventName": "IDQ.MS_DSB_UOPS",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x10",
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"EventName": "IDQ.MS_DSB_CYCLES",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x10",
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"EdgeDetect": "1",
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"EventName": "IDQ.MS_DSB_OCCUR",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x18",
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"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
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"CounterMask": "4",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x18",
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"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x20",
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"EventName": "IDQ.MS_MITE_UOPS",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x24",
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"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles MITE is delivering 4 Uops",
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"CounterMask": "4",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x24",
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"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles MITE is delivering any Uop",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x30",
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"EventName": "IDQ.MS_UOPS",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x30",
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"EventName": "IDQ.MS_CYCLES",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x30",
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"EdgeDetect": "1",
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"EventName": "IDQ.MS_SWITCHES",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Number of uops delivered to IDQ from any path.",
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"EventCode": "0x79",
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"Counter": "0,1,2,3",
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"UMask": "0x3c",
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"EventName": "IDQ.MITE_ALL_UOPS",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
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"EventCode": "0x80",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "ICACHE.HIT",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
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"EventCode": "0x80",
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"Counter": "0,1,2,3",
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"UMask": "0x2",
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"EventName": "ICACHE.MISSES",
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"SampleAfterValue": "200003",
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"BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
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"EventCode": "0x80",
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"Counter": "0,1,2,3",
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"UMask": "0x4",
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"EventName": "ICACHE.IFETCH_STALL",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
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"EventCode": "0x9C",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0x9C",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
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"CounterMask": "4",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0x9C",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
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"CounterMask": "3",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0x9C",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
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"CounterMask": "2",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0x9C",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0x9C",
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"Invert": "1",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"PublicDescription": "Number of DSB to MITE switches.",
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"EventCode": "0xAB",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "DSB2MITE_SWITCHES.COUNT",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Cycles DSB to MITE switches caused delay.",
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"EventCode": "0xAB",
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"Counter": "0,1,2,3",
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"UMask": "0x2",
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"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "DSB Fill encountered > 3 DSB lines.",
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"EventCode": "0xAC",
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"Counter": "0,1,2,3",
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"UMask": "0x8",
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"EventName": "DSB_FILL.EXCEED_DSB_LINES",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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}
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] |