16c00db4bb
Pull AFS fixes from David Howells:
"Here's a set of patches that fix a number of bugs in the in-kernel AFS
client, including:
- Fix directory locking to not use individual page locks for
directory reading/scanning but rather to use a semaphore on the
afs_vnode struct as the directory contents must be read in a single
blob and data from different reads must not be mixed as the entire
contents may be shuffled about between reads.
- Fix address list parsing to handle port specifiers correctly.
- Only give up callback records on a server if we actually talked to
that server (we might not be able to access a server).
- Fix some callback handling bugs, including refcounting,
whole-volume callbacks and when callbacks actually get broken in
response to a CB.CallBack op.
- Fix some server/address rotation bugs, including giving up if we
can't probe a server; giving up if a server says it doesn't have a
volume, but there are more servers to try.
- Fix the decoding of fetched statuses to be OpenAFS compatible.
- Fix the handling of server lookups in Cache Manager ops (such as
CB.InitCallBackState3) to use a UUID if possible and to handle no
server being found.
- Fix a bug in server lookup where not all addresses are compared.
- Fix the non-encryption of calls that prevents some servers from
being accessed (this also requires an AF_RXRPC patch that has
already gone in through the net tree).
There's also a patch that adds tracepoints to log Cache Manager ops
that don't find a matching server, either by UUID or by address"
* tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs:
afs: Fix the non-encryption of calls
afs: Fix CB.CallBack handling
afs: Fix whole-volume callback handling
afs: Fix afs_find_server search loop
afs: Fix the handling of an unfound server in CM operations
afs: Add a tracepoint to record callbacks from unlisted servers
afs: Fix the handling of CB.InitCallBackState3 to find the server by UUID
afs: Fix VNOVOL handling in address rotation
afs: Fix AFSFetchStatus decoder to provide OpenAFS compatibility
afs: Fix server rotation's handling of fileserver probe failure
afs: Fix refcounting in callback registration
afs: Fix giving up callbacks on server destruction
afs: Fix address list parsing
afs: Fix directory page locking
62 lines
No EOL
4.3 KiB
JSON
62 lines
No EOL
4.3 KiB
JSON
[
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
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"EventCode": "0x80",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"PEBScounters": "0,1,2,3",
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"EventName": "ICACHE.HIT",
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"PDIR_COUNTER": "na",
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"SampleAfterValue": "200003",
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"BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
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"EventCode": "0x80",
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"Counter": "0,1,2,3",
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"UMask": "0x2",
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"PEBScounters": "0,1,2,3",
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"EventName": "ICACHE.MISSES",
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"PDIR_COUNTER": "na",
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"SampleAfterValue": "200003",
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"BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",
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"EventCode": "0x80",
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"Counter": "0,1,2,3",
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"UMask": "0x3",
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"PEBScounters": "0,1,2,3",
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"EventName": "ICACHE.ACCESSES",
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"PDIR_COUNTER": "na",
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"SampleAfterValue": "200003",
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"BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.",
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"EventCode": "0xE7",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"PEBScounters": "0,1,2,3",
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"EventName": "MS_DECODED.MS_ENTRY",
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"PDIR_COUNTER": "na",
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"SampleAfterValue": "200003",
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"BriefDescription": "MS decode starts"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.",
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"EventCode": "0xE9",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"PEBScounters": "0,1,2,3",
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"EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
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"PDIR_COUNTER": "na",
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"SampleAfterValue": "200003",
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"BriefDescription": "Decode restrictions due to predicting wrong instruction length"
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}
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] |