16c00db4bb
Pull AFS fixes from David Howells:
"Here's a set of patches that fix a number of bugs in the in-kernel AFS
client, including:
- Fix directory locking to not use individual page locks for
directory reading/scanning but rather to use a semaphore on the
afs_vnode struct as the directory contents must be read in a single
blob and data from different reads must not be mixed as the entire
contents may be shuffled about between reads.
- Fix address list parsing to handle port specifiers correctly.
- Only give up callback records on a server if we actually talked to
that server (we might not be able to access a server).
- Fix some callback handling bugs, including refcounting,
whole-volume callbacks and when callbacks actually get broken in
response to a CB.CallBack op.
- Fix some server/address rotation bugs, including giving up if we
can't probe a server; giving up if a server says it doesn't have a
volume, but there are more servers to try.
- Fix the decoding of fetched statuses to be OpenAFS compatible.
- Fix the handling of server lookups in Cache Manager ops (such as
CB.InitCallBackState3) to use a UUID if possible and to handle no
server being found.
- Fix a bug in server lookup where not all addresses are compared.
- Fix the non-encryption of calls that prevents some servers from
being accessed (this also requires an AF_RXRPC patch that has
already gone in through the net tree).
There's also a patch that adds tracepoints to log Cache Manager ops
that don't find a matching server, either by UUID or by address"
* tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs:
afs: Fix the non-encryption of calls
afs: Fix CB.CallBack handling
afs: Fix whole-volume callback handling
afs: Fix afs_find_server search loop
afs: Fix the handling of an unfound server in CM operations
afs: Add a tracepoint to record callbacks from unlisted servers
afs: Fix the handling of CB.InitCallBackState3 to find the server by UUID
afs: Fix VNOVOL handling in address rotation
afs: Fix AFSFetchStatus decoder to provide OpenAFS compatibility
afs: Fix server rotation's handling of fileserver probe failure
afs: Fix refcounting in callback registration
afs: Fix giving up callbacks on server destruction
afs: Fix address list parsing
afs: Fix directory page locking
294 lines
No EOL
16 KiB
JSON
294 lines
No EOL
16 KiB
JSON
[
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{
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"PEBS": "2",
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"CollectPEBSRecord": "2",
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"PublicDescription": "Counts when a memory load of a uop spans a page boundary (a split) is retired.",
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"EventCode": "0x13",
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"Counter": "0,1,2,3",
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"UMask": "0x2",
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"EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
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"SampleAfterValue": "200003",
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"BriefDescription": "Load uops that split a page (Precise event capable)"
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},
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{
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"PEBS": "2",
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"CollectPEBSRecord": "2",
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"PublicDescription": "Counts when a memory store of a uop spans a page boundary (a split) is retired.",
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"EventCode": "0x13",
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"Counter": "0,1,2,3",
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"UMask": "0x4",
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"EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
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"SampleAfterValue": "200003",
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"BriefDescription": "Store uops that split a page (Precise event capable)"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data.",
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"EventCode": "0xC3",
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"Counter": "0,1,2,3",
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"UMask": "0x2",
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"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
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"SampleAfterValue": "200003",
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"BriefDescription": "Machine clears due to memory ordering issue"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x20000032b7 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000000022 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000003091",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000003010 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000008000 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000004800 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000004000 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000002000 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000001000 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000000800 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts bus lock and split lock requests that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000000400 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts bus lock and split lock requests that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts code reads in uncacheable (UC) memory region that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000000200 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.UC_CODE_RD.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts code reads in uncacheable (UC) memory region that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000000100 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000000080 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000000020 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000000010 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000000008 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000000004 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000000002 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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},
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{
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"CollectPEBSRecord": "1",
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"PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
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"EventCode": "0xB7",
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"MSRValue": "0x2000000001 ",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.NON_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"SampleAfterValue": "100007",
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"BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache and targets non-DRAM system address.",
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"Offcore": "1"
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}
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] |