16c00db4bb
Pull AFS fixes from David Howells:
"Here's a set of patches that fix a number of bugs in the in-kernel AFS
client, including:
- Fix directory locking to not use individual page locks for
directory reading/scanning but rather to use a semaphore on the
afs_vnode struct as the directory contents must be read in a single
blob and data from different reads must not be mixed as the entire
contents may be shuffled about between reads.
- Fix address list parsing to handle port specifiers correctly.
- Only give up callback records on a server if we actually talked to
that server (we might not be able to access a server).
- Fix some callback handling bugs, including refcounting,
whole-volume callbacks and when callbacks actually get broken in
response to a CB.CallBack op.
- Fix some server/address rotation bugs, including giving up if we
can't probe a server; giving up if a server says it doesn't have a
volume, but there are more servers to try.
- Fix the decoding of fetched statuses to be OpenAFS compatible.
- Fix the handling of server lookups in Cache Manager ops (such as
CB.InitCallBackState3) to use a UUID if possible and to handle no
server being found.
- Fix a bug in server lookup where not all addresses are compared.
- Fix the non-encryption of calls that prevents some servers from
being accessed (this also requires an AF_RXRPC patch that has
already gone in through the net tree).
There's also a patch that adds tracepoints to log Cache Manager ops
that don't find a matching server, either by UUID or by address"
* tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs:
afs: Fix the non-encryption of calls
afs: Fix CB.CallBack handling
afs: Fix whole-volume callback handling
afs: Fix afs_find_server search loop
afs: Fix the handling of an unfound server in CM operations
afs: Add a tracepoint to record callbacks from unlisted servers
afs: Fix the handling of CB.InitCallBackState3 to find the server by UUID
afs: Fix VNOVOL handling in address rotation
afs: Fix AFSFetchStatus decoder to provide OpenAFS compatibility
afs: Fix server rotation's handling of fileserver probe failure
afs: Fix refcounting in callback registration
afs: Fix giving up callbacks on server destruction
afs: Fix address list parsing
afs: Fix directory page locking
227 lines
No EOL
9.7 KiB
JSON
227 lines
No EOL
9.7 KiB
JSON
[
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{,
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"EventCode": "0x1E",
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"EventName": "PM_CYC",
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"BriefDescription": "Processor cycles"
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},
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{,
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"EventCode": "0x30010",
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"EventName": "PM_PMC2_OVERFLOW",
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"BriefDescription": "Overflow from counter 2"
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},
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{,
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"EventCode": "0x3C046",
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"EventName": "PM_DATA_FROM_L21_SHR",
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"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load"
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},
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{,
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"EventCode": "0x4D05C",
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"EventName": "PM_DP_QP_FLOP_CMPL",
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"BriefDescription": "Double-Precion or Quad-Precision instruction completed"
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},
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{,
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"EventCode": "0x4E04C",
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"EventName": "PM_DPTEG_FROM_DMEM",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{,
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"EventCode": "0x20016",
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"EventName": "PM_ST_FIN",
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"BriefDescription": "Store finish count. Includes speculative activity"
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},
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{,
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"EventCode": "0x1504A",
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"EventName": "PM_IPTEG_FROM_RL2L3_SHR",
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"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
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},
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{,
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"EventCode": "0x40132",
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"EventName": "PM_MRK_LSU_FIN",
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"BriefDescription": "lsu marked instr PPC finish"
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},
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{,
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"EventCode": "0x3C05C",
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"EventName": "PM_CMPLU_STALL_VFXU",
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"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
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},
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{,
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"EventCode": "0x30066",
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"EventName": "PM_LSU_FIN",
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"BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
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},
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{,
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"EventCode": "0x2011C",
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"EventName": "PM_MRK_NTC_CYC",
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"BriefDescription": "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)"
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},
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{,
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"EventCode": "0x3E048",
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"EventName": "PM_DPTEG_FROM_DL2L3_SHR",
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"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{,
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"EventCode": "0x2E018",
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"EventName": "PM_CMPLU_STALL_VFXLONG",
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"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)"
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},
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{,
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"EventCode": "0x1C04E",
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"EventName": "PM_DATA_FROM_L2MISS_MOD",
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"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load"
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},
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{,
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"EventCode": "0x15048",
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"EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE",
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"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
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},
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{,
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"EventCode": "0x34046",
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"EventName": "PM_INST_FROM_L21_SHR",
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"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x1E058",
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"EventName": "PM_STCX_FAIL",
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"BriefDescription": "stcx failed"
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},
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{,
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"EventCode": "0x300F0",
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"EventName": "PM_ST_MISS_L1",
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"BriefDescription": "Store Missed L1"
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},
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{,
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"EventCode": "0x4C046",
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"EventName": "PM_DATA_FROM_L21_MOD",
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"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load"
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},
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{,
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"EventCode": "0x2504A",
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"EventName": "PM_IPTEG_FROM_RL4",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
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},
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{,
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"EventCode": "0x2003E",
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"EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",
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"BriefDescription": "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)"
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},
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{,
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"EventCode": "0x201E6",
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"EventName": "PM_THRESH_EXC_32",
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"BriefDescription": "Threshold counter exceeded a value of 32"
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},
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{,
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"EventCode": "0x4405C",
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"EventName": "PM_CMPLU_STALL_VDP",
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"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector"
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},
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{,
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"EventCode": "0x4D010",
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"EventName": "PM_PMC1_SAVED",
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"BriefDescription": "PMC1 Rewind Value saved"
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},
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{,
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"EventCode": "0x44042",
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"EventName": "PM_INST_FROM_L3",
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"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x200FE",
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"EventName": "PM_DATA_FROM_L2MISS",
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"BriefDescription": "Demand LD - L2 Miss (not L2 hit)"
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},
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{,
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"EventCode": "0x2D14A",
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"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
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"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
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},
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{,
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"EventCode": "0x10028",
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"EventName": "PM_STALL_END_ICT_EMPTY",
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"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this thread"
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},
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{,
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"EventCode": "0x2504C",
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"EventName": "PM_IPTEG_FROM_MEMORY",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request"
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},
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{,
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"EventCode": "0x4504A",
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"EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE",
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"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request"
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},
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{,
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"EventCode": "0x1404E",
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"EventName": "PM_INST_FROM_L2MISS",
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"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x34042",
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"EventName": "PM_INST_FROM_L3_DISP_CONFLICT",
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"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x4E048",
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"EventName": "PM_DPTEG_FROM_DL2L3_MOD",
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"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{,
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"EventCode": "0x200F0",
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"EventName": "PM_ST_CMPL",
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"BriefDescription": "Stores completed from S2Q (2nd-level store queue)."
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},
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{,
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"EventCode": "0x4E05C",
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"EventName": "PM_LSU_REJECT_LHS",
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"BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)"
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},
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{,
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"EventCode": "0x14044",
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"EventName": "PM_INST_FROM_L3_NO_CONFLICT",
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"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x3E04C",
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"EventName": "PM_DPTEG_FROM_DL4",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{,
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"EventCode": "0x1F15E",
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"EventName": "PM_MRK_PROBE_NOP_CMPL",
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"BriefDescription": "Marked probeNops completed"
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},
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{,
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"EventCode": "0x20018",
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"EventName": "PM_ST_FWD",
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"BriefDescription": "Store forwards that finished"
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},
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{,
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"EventCode": "0x1D142",
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"EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR_CYC",
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"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load"
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},
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{,
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"EventCode": "0x24042",
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"EventName": "PM_INST_FROM_L3_MEPF",
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"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x25046",
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"EventName": "PM_IPTEG_FROM_RL2L3_MOD",
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"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
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},
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{,
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"EventCode": "0x3504A",
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"EventName": "PM_IPTEG_FROM_RMEM",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request"
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},
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{,
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"EventCode": "0x3C05A",
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"EventName": "PM_CMPLU_STALL_VDPLONG",
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"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle"
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},
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{,
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"EventCode": "0x2E01C",
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"EventName": "PM_CMPLU_STALL_TLBIE",
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"BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response from L2"
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}
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] |