16c00db4bb
Pull AFS fixes from David Howells:
"Here's a set of patches that fix a number of bugs in the in-kernel AFS
client, including:
- Fix directory locking to not use individual page locks for
directory reading/scanning but rather to use a semaphore on the
afs_vnode struct as the directory contents must be read in a single
blob and data from different reads must not be mixed as the entire
contents may be shuffled about between reads.
- Fix address list parsing to handle port specifiers correctly.
- Only give up callback records on a server if we actually talked to
that server (we might not be able to access a server).
- Fix some callback handling bugs, including refcounting,
whole-volume callbacks and when callbacks actually get broken in
response to a CB.CallBack op.
- Fix some server/address rotation bugs, including giving up if we
can't probe a server; giving up if a server says it doesn't have a
volume, but there are more servers to try.
- Fix the decoding of fetched statuses to be OpenAFS compatible.
- Fix the handling of server lookups in Cache Manager ops (such as
CB.InitCallBackState3) to use a UUID if possible and to handle no
server being found.
- Fix a bug in server lookup where not all addresses are compared.
- Fix the non-encryption of calls that prevents some servers from
being accessed (this also requires an AF_RXRPC patch that has
already gone in through the net tree).
There's also a patch that adds tracepoints to log Cache Manager ops
that don't find a matching server, either by UUID or by address"
* tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs:
afs: Fix the non-encryption of calls
afs: Fix CB.CallBack handling
afs: Fix whole-volume callback handling
afs: Fix afs_find_server search loop
afs: Fix the handling of an unfound server in CM operations
afs: Add a tracepoint to record callbacks from unlisted servers
afs: Fix the handling of CB.InitCallBackState3 to find the server by UUID
afs: Fix VNOVOL handling in address rotation
afs: Fix AFSFetchStatus decoder to provide OpenAFS compatibility
afs: Fix server rotation's handling of fileserver probe failure
afs: Fix refcounting in callback registration
afs: Fix giving up callbacks on server destruction
afs: Fix address list parsing
afs: Fix directory page locking
165 lines
9.4 KiB
JSON
165 lines
9.4 KiB
JSON
[
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{
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"EventCode": "0xC1",
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"UMask": "0x8",
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"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
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"Counter": "0,1,2,3",
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"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
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"Errata": "BDM30",
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"PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC1",
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"UMask": "0x10",
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"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
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"Counter": "0,1,2,3",
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"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
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"Errata": "BDM30",
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"PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x1",
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"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x2",
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"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x3",
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"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x4",
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x8",
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x10",
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"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x15",
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"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
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"SampleAfterValue": "2000006",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xc7",
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"UMask": "0x20",
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"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x2a",
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"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
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"SampleAfterValue": "2000005",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xC7",
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"UMask": "0x3c",
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"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.PACKED",
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"SampleAfterValue": "2000004",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xCA",
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"UMask": "0x2",
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"BriefDescription": "Number of X87 assists due to output value.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ASSIST.X87_OUTPUT",
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"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xCA",
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"UMask": "0x4",
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"BriefDescription": "Number of X87 assists due to input value.",
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"Counter": "0,1,2,3",
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"EventName": "FP_ASSIST.X87_INPUT",
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"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xCA",
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"UMask": "0x8",
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"BriefDescription": "Number of SIMD FP assists due to Output values",
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"Counter": "0,1,2,3",
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"EventName": "FP_ASSIST.SIMD_OUTPUT",
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"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xCA",
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"UMask": "0x10",
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"BriefDescription": "Number of SIMD FP assists due to input values",
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"Counter": "0,1,2,3",
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"EventName": "FP_ASSIST.SIMD_INPUT",
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"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xCA",
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"UMask": "0x1e",
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"BriefDescription": "Cycles with any input/output SSE or FP assist",
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"Counter": "0,1,2,3",
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"EventName": "FP_ASSIST.ANY",
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"CounterMask": "1",
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"PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3"
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}
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] |