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perf-eh_elf/pmu-events/arch/x86/bonnell/cache.json
Linus Torvalds 16c00db4bb Merge tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs 
Pull AFS fixes from David Howells:
 "Here's a set of patches that fix a number of bugs in the in-kernel AFS
  client, including:

   - Fix directory locking to not use individual page locks for
     directory reading/scanning but rather to use a semaphore on the
     afs_vnode struct as the directory contents must be read in a single
     blob and data from different reads must not be mixed as the entire
     contents may be shuffled about between reads.

   - Fix address list parsing to handle port specifiers correctly.

   - Only give up callback records on a server if we actually talked to
     that server (we might not be able to access a server).

   - Fix some callback handling bugs, including refcounting,
     whole-volume callbacks and when callbacks actually get broken in
     response to a CB.CallBack op.

   - Fix some server/address rotation bugs, including giving up if we
     can't probe a server; giving up if a server says it doesn't have a
     volume, but there are more servers to try.

   - Fix the decoding of fetched statuses to be OpenAFS compatible.

   - Fix the handling of server lookups in Cache Manager ops (such as
     CB.InitCallBackState3) to use a UUID if possible and to handle no
     server being found.

   - Fix a bug in server lookup where not all addresses are compared.

   - Fix the non-encryption of calls that prevents some servers from
     being accessed (this also requires an AF_RXRPC patch that has
     already gone in through the net tree).

  There's also a patch that adds tracepoints to log Cache Manager ops
  that don't find a matching server, either by UUID or by address"

* tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs:
  afs: Fix the non-encryption of calls
  afs: Fix CB.CallBack handling
  afs: Fix whole-volume callback handling
  afs: Fix afs_find_server search loop
  afs: Fix the handling of an unfound server in CM operations
  afs: Add a tracepoint to record callbacks from unlisted servers
  afs: Fix the handling of CB.InitCallBackState3 to find the server by UUID
  afs: Fix VNOVOL handling in address rotation
  afs: Fix AFSFetchStatus decoder to provide OpenAFS compatibility
  afs: Fix server rotation's handling of fileserver probe failure
  afs: Fix refcounting in callback registration
  afs: Fix giving up callbacks on server destruction
  afs: Fix address list parsing
  afs: Fix directory page locking
2018-05-15 10:48:36 -07:00

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[
{
"EventCode": "0x21",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_ADS.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Cycles L2 address bus is in use."
},
{
"EventCode": "0x22",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_DBUS_BUSY.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Cycles the L2 cache data bus is busy."
},
{
"EventCode": "0x23",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_DBUS_BUSY_RD.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Cycles the L2 transfers data to the core."
},
{
"EventCode": "0x24",
"Counter": "0,1",
"UMask": "0x70",
"EventName": "L2_LINES_IN.SELF.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache misses."
},
{
"EventCode": "0x24",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_LINES_IN.SELF.DEMAND",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache misses."
},
{
"EventCode": "0x24",
"Counter": "0,1",
"UMask": "0x50",
"EventName": "L2_LINES_IN.SELF.PREFETCH",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache misses."
},
{
"EventCode": "0x25",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_M_LINES_IN.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache line modifications."
},
{
"EventCode": "0x26",
"Counter": "0,1",
"UMask": "0x70",
"EventName": "L2_LINES_OUT.SELF.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache lines evicted."
},
{
"EventCode": "0x26",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_LINES_OUT.SELF.DEMAND",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache lines evicted."
},
{
"EventCode": "0x26",
"Counter": "0,1",
"UMask": "0x50",
"EventName": "L2_LINES_OUT.SELF.PREFETCH",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache lines evicted."
},
{
"EventCode": "0x27",
"Counter": "0,1",
"UMask": "0x70",
"EventName": "L2_M_LINES_OUT.SELF.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "Modified lines evicted from the L2 cache"
},
{
"EventCode": "0x27",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_M_LINES_OUT.SELF.DEMAND",
"SampleAfterValue": "200000",
"BriefDescription": "Modified lines evicted from the L2 cache"
},
{
"EventCode": "0x27",
"Counter": "0,1",
"UMask": "0x50",
"EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
"SampleAfterValue": "200000",
"BriefDescription": "Modified lines evicted from the L2 cache"
},
{
"EventCode": "0x28",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_IFETCH.SELF.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cacheable instruction fetch requests"
},
{
"EventCode": "0x28",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_IFETCH.SELF.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cacheable instruction fetch requests"
},
{
"EventCode": "0x28",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_IFETCH.SELF.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cacheable instruction fetch requests"
},
{
"EventCode": "0x28",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_IFETCH.SELF.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cacheable instruction fetch requests"
},
{
"EventCode": "0x28",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_IFETCH.SELF.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cacheable instruction fetch requests"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x74",
"EventName": "L2_LD.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x71",
"EventName": "L2_LD.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x78",
"EventName": "L2_LD.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x72",
"EventName": "L2_LD.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x7f",
"EventName": "L2_LD.SELF.ANY.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_LD.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_LD.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_LD.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_LD.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_LD.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x54",
"EventName": "L2_LD.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x51",
"EventName": "L2_LD.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x58",
"EventName": "L2_LD.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x52",
"EventName": "L2_LD.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x29",
"Counter": "0,1",
"UMask": "0x5f",
"EventName": "L2_LD.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache reads"
},
{
"EventCode": "0x2A",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_ST.SELF.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 store requests"
},
{
"EventCode": "0x2A",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_ST.SELF.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 store requests"
},
{
"EventCode": "0x2A",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_ST.SELF.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 store requests"
},
{
"EventCode": "0x2A",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_ST.SELF.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 store requests"
},
{
"EventCode": "0x2A",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_ST.SELF.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 store requests"
},
{
"EventCode": "0x2B",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_LOCK.SELF.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 locked accesses"
},
{
"EventCode": "0x2B",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_LOCK.SELF.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 locked accesses"
},
{
"EventCode": "0x2B",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_LOCK.SELF.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 locked accesses"
},
{
"EventCode": "0x2B",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_LOCK.SELF.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 locked accesses"
},
{
"EventCode": "0x2B",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_LOCK.SELF.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 locked accesses"
},
{
"EventCode": "0x2C",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_DATA_RQSTS.SELF.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All data requests from the L1 data cache"
},
{
"EventCode": "0x2C",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_DATA_RQSTS.SELF.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All data requests from the L1 data cache"
},
{
"EventCode": "0x2C",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_DATA_RQSTS.SELF.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All data requests from the L1 data cache"
},
{
"EventCode": "0x2C",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_DATA_RQSTS.SELF.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All data requests from the L1 data cache"
},
{
"EventCode": "0x2C",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_DATA_RQSTS.SELF.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "All data requests from the L1 data cache"
},
{
"EventCode": "0x2D",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_LD_IFETCH.SELF.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All read requests from L1 instruction and data caches"
},
{
"EventCode": "0x2D",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_LD_IFETCH.SELF.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All read requests from L1 instruction and data caches"
},
{
"EventCode": "0x2D",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_LD_IFETCH.SELF.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All read requests from L1 instruction and data caches"
},
{
"EventCode": "0x2D",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_LD_IFETCH.SELF.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "All read requests from L1 instruction and data caches"
},
{
"EventCode": "0x2D",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_LD_IFETCH.SELF.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "All read requests from L1 instruction and data caches"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x74",
"EventName": "L2_RQSTS.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x71",
"EventName": "L2_RQSTS.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x78",
"EventName": "L2_RQSTS.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x72",
"EventName": "L2_RQSTS.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x7f",
"EventName": "L2_RQSTS.SELF.ANY.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x54",
"EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x51",
"EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x58",
"EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x52",
"EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x5f",
"EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache requests"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache demand requests from this core that missed the L2"
},
{
"EventCode": "0x2E",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_RQSTS.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "L2 cache demand requests from this core"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x74",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x71",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x78",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x72",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x7f",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x44",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x41",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x42",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x4f",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x54",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x51",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x58",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x52",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x30",
"Counter": "0,1",
"UMask": "0x5f",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
"BriefDescription": "Rejected L2 cache requests"
},
{
"EventCode": "0x32",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "L2_NO_REQ.SELF",
"SampleAfterValue": "200000",
"BriefDescription": "Cycles no L2 cache requests are pending"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0xa1",
"EventName": "L1D_CACHE.LD",
"SampleAfterValue": "2000000",
"BriefDescription": "L1 Cacheable Data Reads"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0xa2",
"EventName": "L1D_CACHE.ST",
"SampleAfterValue": "2000000",
"BriefDescription": "L1 Cacheable Data Writes"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0x83",
"EventName": "L1D_CACHE.ALL_REF",
"SampleAfterValue": "2000000",
"BriefDescription": "L1 Data reads and writes"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0xa3",
"EventName": "L1D_CACHE.ALL_CACHE_REF",
"SampleAfterValue": "2000000",
"BriefDescription": "L1 Data Cacheable reads and writes"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "L1D_CACHE.REPL",
"SampleAfterValue": "200000",
"BriefDescription": "L1 Data line replacements"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0x48",
"EventName": "L1D_CACHE.REPLM",
"SampleAfterValue": "200000",
"BriefDescription": "Modified cache lines allocated in the L1 data cache"
},
{
"EventCode": "0x40",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "L1D_CACHE.EVICT",
"SampleAfterValue": "200000",
"BriefDescription": "Modified cache lines evicted from the L1 data cache"
},
{
"EventCode": "0xCB",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"SampleAfterValue": "200000",
"BriefDescription": "Retired loads that hit the L2 cache (precise event)."
},
{
"EventCode": "0xCB",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"SampleAfterValue": "10000",
"BriefDescription": "Retired loads that miss the L2 cache"
}
]
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