16c00db4bb
Pull AFS fixes from David Howells:
"Here's a set of patches that fix a number of bugs in the in-kernel AFS
client, including:
- Fix directory locking to not use individual page locks for
directory reading/scanning but rather to use a semaphore on the
afs_vnode struct as the directory contents must be read in a single
blob and data from different reads must not be mixed as the entire
contents may be shuffled about between reads.
- Fix address list parsing to handle port specifiers correctly.
- Only give up callback records on a server if we actually talked to
that server (we might not be able to access a server).
- Fix some callback handling bugs, including refcounting,
whole-volume callbacks and when callbacks actually get broken in
response to a CB.CallBack op.
- Fix some server/address rotation bugs, including giving up if we
can't probe a server; giving up if a server says it doesn't have a
volume, but there are more servers to try.
- Fix the decoding of fetched statuses to be OpenAFS compatible.
- Fix the handling of server lookups in Cache Manager ops (such as
CB.InitCallBackState3) to use a UUID if possible and to handle no
server being found.
- Fix a bug in server lookup where not all addresses are compared.
- Fix the non-encryption of calls that prevents some servers from
being accessed (this also requires an AF_RXRPC patch that has
already gone in through the net tree).
There's also a patch that adds tracepoints to log Cache Manager ops
that don't find a matching server, either by UUID or by address"
* tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs:
afs: Fix the non-encryption of calls
afs: Fix CB.CallBack handling
afs: Fix whole-volume callback handling
afs: Fix afs_find_server search loop
afs: Fix the handling of an unfound server in CM operations
afs: Add a tracepoint to record callbacks from unlisted servers
afs: Fix the handling of CB.InitCallBackState3 to find the server by UUID
afs: Fix VNOVOL handling in address rotation
afs: Fix AFSFetchStatus decoder to provide OpenAFS compatibility
afs: Fix server rotation's handling of fileserver probe failure
afs: Fix refcounting in callback registration
afs: Fix giving up callbacks on server destruction
afs: Fix address list parsing
afs: Fix directory page locking
107 lines
4.7 KiB
JSON
107 lines
4.7 KiB
JSON
[
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{,
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"EventCode": "0x300F4",
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"EventName": "PM_THRD_CONC_RUN_INST",
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"BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
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},
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{,
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"EventCode": "0x1E056",
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"EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
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"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion"
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},
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{,
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"EventCode": "0x4D016",
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"EventName": "PM_CMPLU_STALL_FXLONG",
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"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)"
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},
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{,
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"EventCode": "0x2D016",
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"EventName": "PM_CMPLU_STALL_FXU",
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"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
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},
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{,
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"EventCode": "0x4D12A",
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"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
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"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
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},
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{,
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"EventCode": "0x1003C",
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"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
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"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3"
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},
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{,
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"EventCode": "0x4C014",
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"EventName": "PM_CMPLU_STALL_LMQ_FULL",
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"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full"
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},
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{,
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"EventCode": "0x14048",
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"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
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"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x4D014",
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"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
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"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish"
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},
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{,
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"EventCode": "0x2404A",
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"EventName": "PM_INST_FROM_RL4",
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"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x1404A",
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"EventName": "PM_INST_FROM_RL2L3_SHR",
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"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x401EA",
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"EventName": "PM_THRESH_EXC_128",
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"BriefDescription": "Threshold counter exceeded a value of 128"
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},
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{,
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"EventCode": "0x400F6",
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"EventName": "PM_BR_MPRED_CMPL",
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"BriefDescription": "Number of Branch Mispredicts"
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},
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{,
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"EventCode": "0x2F140",
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"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{,
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"EventCode": "0x101E6",
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"EventName": "PM_THRESH_EXC_4096",
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"BriefDescription": "Threshold counter exceed a count of 4096"
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},
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{,
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"EventCode": "0x3F14A",
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"EventName": "PM_MRK_DPTEG_FROM_RMEM",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{,
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"EventCode": "0x4C016",
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"EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
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"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict"
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},
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{,
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"EventCode": "0x2C01A",
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"EventName": "PM_CMPLU_STALL_LHS",
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"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data"
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},
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{,
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"EventCode": "0x401E4",
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"EventName": "PM_MRK_DTLB_MISS",
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"BriefDescription": "Marked dtlb miss"
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},
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{,
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"EventCode": "0x24046",
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"EventName": "PM_INST_FROM_RL2L3_MOD",
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"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
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},
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{,
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"EventCode": "0x1002A",
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"EventName": "PM_CMPLU_STALL_LARX",
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"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"
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}
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] |