16c00db4bb
Pull AFS fixes from David Howells:
"Here's a set of patches that fix a number of bugs in the in-kernel AFS
client, including:
- Fix directory locking to not use individual page locks for
directory reading/scanning but rather to use a semaphore on the
afs_vnode struct as the directory contents must be read in a single
blob and data from different reads must not be mixed as the entire
contents may be shuffled about between reads.
- Fix address list parsing to handle port specifiers correctly.
- Only give up callback records on a server if we actually talked to
that server (we might not be able to access a server).
- Fix some callback handling bugs, including refcounting,
whole-volume callbacks and when callbacks actually get broken in
response to a CB.CallBack op.
- Fix some server/address rotation bugs, including giving up if we
can't probe a server; giving up if a server says it doesn't have a
volume, but there are more servers to try.
- Fix the decoding of fetched statuses to be OpenAFS compatible.
- Fix the handling of server lookups in Cache Manager ops (such as
CB.InitCallBackState3) to use a UUID if possible and to handle no
server being found.
- Fix a bug in server lookup where not all addresses are compared.
- Fix the non-encryption of calls that prevents some servers from
being accessed (this also requires an AF_RXRPC patch that has
already gone in through the net tree).
There's also a patch that adds tracepoints to log Cache Manager ops
that don't find a matching server, either by UUID or by address"
* tag 'afs-fixes-20180514' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs:
afs: Fix the non-encryption of calls
afs: Fix CB.CallBack handling
afs: Fix whole-volume callback handling
afs: Fix afs_find_server search loop
afs: Fix the handling of an unfound server in CM operations
afs: Add a tracepoint to record callbacks from unlisted servers
afs: Fix the handling of CB.InitCallBackState3 to find the server by UUID
afs: Fix VNOVOL handling in address rotation
afs: Fix AFSFetchStatus decoder to provide OpenAFS compatibility
afs: Fix server rotation's handling of fileserver probe failure
afs: Fix refcounting in callback registration
afs: Fix giving up callbacks on server destruction
afs: Fix address list parsing
afs: Fix directory page locking
177 lines
10 KiB
JSON
177 lines
10 KiB
JSON
[
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{,
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"EventCode": "0x4c048",
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"EventName": "PM_DATA_FROM_DL2L3_MOD",
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"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x3c048",
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"EventName": "PM_DATA_FROM_DL2L3_SHR",
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"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x3c04c",
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"EventName": "PM_DATA_FROM_DL4",
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"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x1c042",
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"EventName": "PM_DATA_FROM_L2",
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"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x200fe",
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"EventName": "PM_DATA_FROM_L2MISS",
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"BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x1c04e",
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"EventName": "PM_DATA_FROM_L2MISS_MOD",
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"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x3c040",
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"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
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"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x4c040",
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"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
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"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x2c040",
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"EventName": "PM_DATA_FROM_L2_MEPF",
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"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x1c040",
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"EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
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"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x4c042",
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"EventName": "PM_DATA_FROM_L3",
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"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x300fe",
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"EventName": "PM_DATA_FROM_L3MISS",
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"BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x4c04e",
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"EventName": "PM_DATA_FROM_L3MISS_MOD",
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"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x3c042",
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"EventName": "PM_DATA_FROM_L3_DISP_CONFLICT",
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"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x2c042",
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"EventName": "PM_DATA_FROM_L3_MEPF",
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"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x1c044",
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"EventName": "PM_DATA_FROM_L3_NO_CONFLICT",
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"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x1c04c",
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"EventName": "PM_DATA_FROM_LL4",
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"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x4c04a",
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"EventName": "PM_DATA_FROM_OFF_CHIP_CACHE",
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"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x1c048",
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"EventName": "PM_DATA_FROM_ON_CHIP_CACHE",
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"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x2c046",
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"EventName": "PM_DATA_FROM_RL2L3_MOD",
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"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x1c04a",
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"EventName": "PM_DATA_FROM_RL2L3_SHR",
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"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
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"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
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},
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{,
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"EventCode": "0x3001a",
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"EventName": "PM_DATA_TABLEWALK_CYC",
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"BriefDescription": "Tablwalk Cycles (could be 1 or 2 active)",
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"PublicDescription": "Data Tablewalk Active"
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},
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{,
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"EventCode": "0x4e04e",
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"EventName": "PM_DPTEG_FROM_L3MISS",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0xd094",
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"EventName": "PM_DSLB_MISS",
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"BriefDescription": "Data SLB Miss - Total of all segment sizes",
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"PublicDescription": "Data SLB Miss - Total of all segment sizesData SLB misses"
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},
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{,
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"EventCode": "0x1002c",
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"EventName": "PM_L1_DCACHE_RELOADED_ALL",
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"BriefDescription": "L1 data cache reloaded for demand or prefetch",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x300f6",
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"EventName": "PM_L1_DCACHE_RELOAD_VALID",
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"BriefDescription": "DL1 reloaded due to Demand Load",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x3e054",
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"EventName": "PM_LD_MISS_L1",
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"BriefDescription": "Load Missed L1",
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"PublicDescription": ""
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},
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{,
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"EventCode": "0x100ee",
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"EventName": "PM_LD_REF_L1",
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"BriefDescription": "All L1 D cache load references counted at finish, gated by reject",
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"PublicDescription": "Load Ref count combined for all units"
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},
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{,
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"EventCode": "0x300f0",
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"EventName": "PM_ST_MISS_L1",
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"BriefDescription": "Store Missed L1",
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"PublicDescription": ""
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},
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]
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