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216 lines
9.9 KiB
TeX
216 lines
9.9 KiB
TeX
\documentclass{article}
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\usepackage[fancyhdr,pdf]{latex2man}
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\input{common.tex}
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\begin{document}
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\begin{Name}{3}{libunwind-ia64}{David Mosberger-Tang}{Programming Library}{IA-64-specific support in libunwind}libunwind-ia64 -- IA-64-specific support in libunwind
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\end{Name}
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\section{Introduction}
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The IA-64 version of \Prog{libunwind} uses a platform-string of
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\texttt{ia64} and, at least in theory, should be able to support all
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operating systems adhering to the processor-specific ABI defined for
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the Itanium Processor Family. This includes both little-endian Linux
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and big-endian HP-UX. Furthermore, to make it possible for a single
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library to unwind both 32- and 64-bit targets, the type
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\Type{unw\_word\_t} is always defined to be 64 bits wide (independent
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of the natural word-size of the host). Having said that, the current
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implementation has been tested only with IA-64 Linux.
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When targeting IA-64, the \Prog{libunwind} header file defines the
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macro \Const{UNW\_TARGET\_IA64} as 1 and the macro \Const{UNW\_TARGET}
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as ``ia64'' (without the quotation marks). The former makes it
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possible for platform-dependent unwind code to use
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conditional-compilation to select an appropriate implementation. The
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latter is useful for stringification purposes and to construct
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target-platform-specific symbols.
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One special feature of IA-64 is the use of NaT bits to support
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speculative execution. Often, NaT bits are thought of as the ``65-th
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bit'' of a general register. However, to make everything fit into
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64-bit wide \Type{unw\_word\_t} values, \Prog{libunwind} treats the
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NaT-bits like separate boolean registers, whose 64-bit value is either
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TRUE (non-zero) or FALSE (zero).
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\section{Machine-State}
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The machine-state (set of registers) that is accessible through
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\Prog{libunwind} depends on the type of stack frame that a cursor
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points to. For normal frames, all ``preserved'' (callee-saved)
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registers are accessible. For signal-trampoline frames, all registers
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(including ``scratch'' (caller-saved) registers) are accessible. Most
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applications do not have to worry a-priori about which registers are
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accessible when. In case of doubt, it is always safe to \emph{try} to
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access a register (via \Func{unw\_get\_reg}() or
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\Func{unw\_get\_fpreg}()) and if the register isn't accessible, the
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call will fail with a return-value of \texttt{-}\Const{UNW\_EBADREG}.
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As a special exception to the above general rule, scratch registers
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\texttt{r15}-\texttt{r18} are always accessible, even in normal
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frames. This makes it possible to pass arguments, e.g., to exception
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handlers.
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For a detailed description of the IA-64 register usage convention,
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please see the ``Itanium Software Conventions and Runtime Architecture
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Guide'', available at:
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\begin{center}
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\URL{http://www.intel.com/design/itanium/downloads/245358.htm}
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\end{center}
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\section{Register Names}
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The IA-64-version of \Prog{libunwind} defines three kinds of register
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name macros: frame-register macros, normal register macros, and
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convenience macros. Below, we describe each kind in turn:
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\subsection{Frame-register Macros}
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Frame-registers are special (pseudo) registers because they always
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have a valid value, even though sometimes they do not get saved
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explicitly (e.g., if a memory stack frame is 16 bytes in size, the
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previous stack-pointer value can be calculated simply as
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\texttt{sp+16}, so there is no need to save the stack-pointer
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explicitly). Moreover, the set of frame register values uniquely
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identifies a stack frame. The IA-64 architecture defines two stacks
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(a memory and a register stack). Including the instruction-pointer
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(IP), this means there are three frame registers:
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\begin{Description}
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\item[\Const{UNW\_IA64\_IP}:] Contains the instruction pointer (IP, or
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``program counter'') of the current stack frame. Given this value,
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the remaining machine-state corresponds to the register-values that
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were present in the CPU when it was just about to execute the
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instruction pointed to by \Const{UNW\_IA64\_IP}. Bits 0 and 1 of
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this frame-register encode the slot number of the instruction.
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\textbf{Note:} Due to the way the call instruction works on IA-64,
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the slot number is usually zero, but can be non-zero, e.g., in the
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stack-frame of a signal-handler trampoline.
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\item[\Const{UNW\_IA64\_SP}:] Contains the (memory) stack-pointer
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value (SP). This frame-register is read-only.
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\item[\Const{UNW\_IA64\_BSP}:] Contains the register backing-store
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pointer (BSP). This frame-register is read-only. \textbf{Note:}
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the value in this register is equal to the contents of register
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\texttt{ar.bsp} at the time the instruction at \Const{UNW\_IA64\_IP}
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was about to begin execution.
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\end{Description}
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\subsection{Normal Register Macros}
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The following normal register name macros are available:
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\begin{Description}
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\item[\Const{UNW\_IA64\_GR}:] The base-index for general (integer)
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registers. Add an index in the range from 0..127 to get a
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particular general register. For example, to access \texttt{r4},
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the index \Const{UNW\_IA64\_GR}\texttt{+4} should be used.
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Registers \texttt{r0} and \texttt{r1} (\texttt{gp}) are read-only,
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and any attempt to write them will result in an error
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(\texttt{-}\Const{UNW\_EREADONLYREG}). Even though \texttt{r1} is
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read-only, \Prog{libunwind} will automatically adjust its value if
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the instruction-pointer (\Const{UNW\_IA64\_IP}) is modified. For
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example, if \Const{UNW\_IA64\_IP} is set to a value inside a
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function \Func{func}(), then reading
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\Const{UNW\_IA64\_GR}\texttt{+1} will return the global-pointer
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value for this function.
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\item[\Const{UNW\_IA64\_NAT}:] The base-index for the NaT bits of the
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general (integer) registers. A non-zero value in these registers
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corresponds to a set NaT-bit. Add an index in the range from 0..127
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to get a particular NaT-bit register. For example, to access the
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NaT bit of \texttt{r4}, the index \Const{UNW\_IA64\_NAT}\texttt{+4}
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should be used.
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\item[\Const{UNW\_IA64\_FR}:] The base-index for floating-point
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registers. Add an index in the range from 0..127 to get a
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particular floating-point register. For example, to access
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\texttt{f2}, the index \Const{UNW\_IA64\_FR}\texttt{+2} should be
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used. Registers \texttt{f0} and \texttt{f1} are read-only, and any
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attempt to write to indices \Const{UNW\_IA64\_FR}\texttt{+0} or
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\Const{UNW\_IA64\_FR}\texttt{+1} will result in an error
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(\texttt{-}\Const{UNW\_EREADONLYREG}).
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\item[\Const{UNW\_IA64\_AR}:] The base-index for application
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registers. Add an index in the range from 0..127 to get a
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particular application register. For example, to access
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\texttt{ar40}, the index \Const{UNW\_IA64\_AR}\texttt{+40} should be
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used. The IA-64 architecture defines several application registers
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as ``reserved for future use''. Attempting to access such registers
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results in an error (\texttt{-}\Const{UNW\_EBADREG}).
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\item[\Const{UNW\_IA64\_BR}:] The base-index for branch registers.
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Add an index in the range from 0..7 to get a particular branch
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register. For example, to access \texttt{b6}, the index
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\Const{UNW\_IA64\_BR}\texttt{+6} should be used.
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\item[\Const{UNW\_IA64\_PR}:] Contains the set of predicate registers.
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This 64-bit wide register contains registers \texttt{p0} through
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\texttt{p63} in the ``broad-side'' format (i.e., \texttt{p0}
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corresponds to bit 0, \texttt{p1} to bit 1, and so on).
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\item[\Const{UNW\_IA64\_CFM}:] Contains the current-frame-mask
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register.
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\end{Description}
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\subsection{Convenience Macros}
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Convenience macros are simply aliases for certain frequently used
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registers:
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\begin{Description}
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\item[\Const{UNW\_IA64\_GP}:] Alias for \Const{UNW\_IA64\_GR}\texttt{+1},
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the global-pointer register.
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\item[\Const{UNW\_IA64\_TP}:] Alias for \Const{UNW\_IA64\_GR}\texttt{+13},
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the thread-pointer register.
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\item[\Const{UNW\_IA64\_AR\_RSC}:] Alias for \Const{UNW\_IA64\_GR}\texttt{+16},
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the register-stack configuration register.
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\item[\Const{UNW\_IA64\_AR\_BSP}:] Alias for
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\Const{UNW\_IA64\_GR}\texttt{+17}. This register index accesses the
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value of register \texttt{ar.bsp} as of the time it was last saved
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explicitly. This is rarely what you want. Normally, you'll want to
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use \Const{UNW\_IA64\_BSP} instead.
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\item[\Const{UNW\_IA64\_AR\_BSPSTORE}:] Alias for \Const{UNW\_IA64\_GR}\texttt{+18},
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the register-backing store write pointer.
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\item[\Const{UNW\_IA64\_AR\_RNAT}:] Alias for \Const{UNW\_IA64\_GR}\texttt{+19},
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the register-backing store NaT-collection register.
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\item[\Const{UNW\_IA64\_AR\_CCV}:] Alias for \Const{UNW\_IA64\_GR}\texttt{+32},
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the compare-and-swap value register.
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\item[\Const{UNW\_IA64\_AR\_CSD}:] Alias for \Const{UNW\_IA64\_GR}\texttt{+25},
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the compare-and-swap-data register (used by 16-byte atomic operations).
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\item[\Const{UNW\_IA64\_AR\_UNAT}:] Alias for \Const{UNW\_IA64\_GR}\texttt{+36},
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the user NaT-collection register.
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\item[\Const{UNW\_IA64\_AR\_FPSR}:] Alias for \Const{UNW\_IA64\_GR}\texttt{+40},
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the floating-point status (and control) register.
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\item[\Const{UNW\_IA64\_AR\_PFS}:] Alias for \Const{UNW\_IA64\_GR}\texttt{+64},
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the previous frame-state register.
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\item[\Const{UNW\_IA64\_AR\_LC}:] Alias for \Const{UNW\_IA64\_GR}\texttt{+65}
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the loop-count register.
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\item[\Const{UNW\_IA64\_AR\_EC}:] Alias for \Const{UNW\_IA64\_GR}\texttt{+66},
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the epilogue-count register.
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\end{Description}
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\section{The Unwind-Context Type}
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On IA-64, \Type{unw\_context\_t} is simply an alias for
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\Type{ucontext\_t} (as defined by the Single UNIX Spec). This implies
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that it is possible to initialize a value of this type not just with
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\Func{unw\_getcontext}(), but also with \Func{getcontext}(), for
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example. However, since this is an IA-64-specific extension to
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\Prog{libunwind}, portable code should not rely on this equivalence.
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\section{See Also}
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\SeeAlso{libunwind(3)}
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\section{Author}
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\noindent
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David Mosberger-Tang\\
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Hewlett-Packard Labs\\
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Palo-Alto, CA 94304\\
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Email: \Email{davidm@hpl.hp.com}\\
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WWW: \URL{http://www.hpl.hp.com/research/linux/libunwind/}.
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\LatexManEnd
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\end{document}
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