mirror of
https://github.com/tobast/libunwind-eh_elf.git
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Rename: src/ia64/Gregs-ia64.c -> src/ia64/Gregs.c
(Logical change 1.241)
This commit is contained in:
homeip.net!davidm
parent
8f58a1cf9c
commit
b3f681603b
1 changed files with 583 additions and 0 deletions
583
src/ia64/Gregs.c
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583
src/ia64/Gregs.c
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/* libunwind - a platform-independent unwind library
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Copyright (C) 2001-2004 Hewlett-Packard Co
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
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This file is part of libunwind.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#include <assert.h>
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#include <stddef.h>
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#include "offsets.h"
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#include "regs.h"
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#include "unwind_i.h"
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static inline ia64_loc_t
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linux_scratch_loc (struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr)
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{
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#if !defined(UNW_LOCAL_ONLY) || defined(__linux)
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unw_word_t addr = c->sigcontext_addr, flags, tmp_addr;
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int i;
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if (c->last_abi_marker == ABI_MARKER_LINUX_SIGTRAMP
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|| c->last_abi_marker == ABI_MARKER_OLD_LINUX_SIGTRAMP)
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{
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switch (reg)
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{
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case UNW_IA64_NAT + 2 ... UNW_IA64_NAT + 3:
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case UNW_IA64_NAT + 8 ... UNW_IA64_NAT + 31:
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/* Linux sigcontext contains the NaT bit of scratch register
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N in bit position N of the sc_nat member. */
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*nat_bitnr = (reg - UNW_IA64_NAT);
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addr += LINUX_SC_NAT_OFF;
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break;
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case UNW_IA64_GR + 2 ... UNW_IA64_GR + 3:
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case UNW_IA64_GR + 8 ... UNW_IA64_GR + 31:
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addr += LINUX_SC_GR_OFF + 8 * (reg - UNW_IA64_GR);
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break;
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case UNW_IA64_FR + 6 ... UNW_IA64_FR + 15:
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addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR);
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return IA64_LOC_ADDR (addr, IA64_LOC_TYPE_FP);
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case UNW_IA64_FR + 32 ... UNW_IA64_FR + 127:
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if (ia64_get (c, IA64_LOC_ADDR (addr + LINUX_SC_FLAGS_OFF, 0),
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&flags) < 0)
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return IA64_NULL_LOC;
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if (!(flags & IA64_SC_FLAG_FPH_VALID))
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{
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/* initialize fph partition: */
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tmp_addr = addr + LINUX_SC_FR_OFF + 32*16;
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for (i = 32; i < 128; ++i, tmp_addr += 16)
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if (ia64_putfp (c, IA64_LOC_ADDR (tmp_addr, 0),
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unw.read_only.f0) < 0)
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return IA64_NULL_LOC;
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/* mark fph partition as valid: */
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if (ia64_put (c, IA64_LOC_ADDR (addr + LINUX_SC_FLAGS_OFF, 0),
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flags | IA64_SC_FLAG_FPH_VALID) < 0)
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return IA64_NULL_LOC;
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}
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addr += LINUX_SC_FR_OFF + 16 * (reg - UNW_IA64_FR);
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return IA64_LOC_ADDR (addr, IA64_LOC_TYPE_FP);
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case UNW_IA64_BR + 0: addr += LINUX_SC_BR_OFF + 0; break;
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case UNW_IA64_BR + 6: addr += LINUX_SC_BR_OFF + 6*8; break;
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case UNW_IA64_BR + 7: addr += LINUX_SC_BR_OFF + 7*8; break;
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case UNW_IA64_AR_RSC: addr += LINUX_SC_AR_RSC_OFF; break;
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case UNW_IA64_AR_CSD: addr += LINUX_SC_AR_CSD_OFF; break;
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case UNW_IA64_AR_SSD: addr += LINUX_SC_AR_SSD_OFF; break;
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case UNW_IA64_AR_CCV: addr += LINUX_SC_AR_CCV; break;
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default:
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return IA64_REG_LOC (c, reg);
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}
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return IA64_LOC_ADDR (addr, 0);
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}
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else
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{
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int is_nat = 0;
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if ((unsigned) (reg - UNW_IA64_NAT) < 128)
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{
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is_nat = 1;
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reg -= (UNW_IA64_NAT - UNW_IA64_GR);
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}
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if (c->last_abi_marker == ABI_MARKER_LINUX_INTERRUPT)
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{
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switch (reg)
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{
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case UNW_IA64_BR + 6 ... UNW_IA64_BR + 7:
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addr += LINUX_PT_B6_OFF + 8 * (reg - (UNW_IA64_BR + 6));
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break;
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case UNW_IA64_AR_CSD: addr += LINUX_PT_CSD_OFF; break;
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case UNW_IA64_AR_SSD: addr += LINUX_PT_SSD_OFF; break;
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case UNW_IA64_GR + 8 ... UNW_IA64_GR + 11:
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addr += LINUX_PT_R8_OFF + 8 * (reg - (UNW_IA64_GR + 8));
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break;
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case UNW_IA64_AR_RSC: addr += LINUX_PT_RSC_OFF; break;
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case UNW_IA64_BR + 0: addr += LINUX_PT_B0_OFF; break;
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case UNW_IA64_GR + 1: addr += LINUX_PT_R1_OFF; break;
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case UNW_IA64_GR + 2: addr += LINUX_PT_R2_OFF; break;
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case UNW_IA64_GR + 3: addr += LINUX_PT_R3_OFF; break;
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case UNW_IA64_GR + 16 ... UNW_IA64_GR + 31:
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addr += LINUX_PT_R16_OFF + 8 * (reg - (UNW_IA64_GR + 16));
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break;
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case UNW_IA64_AR_CCV: addr += LINUX_PT_CCV_OFF; break;
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case UNW_IA64_FR + 6 ... UNW_IA64_FR + 11:
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addr += LINUX_PT_F6_OFF + 16 * (reg - (UNW_IA64_FR + 6));
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return IA64_LOC_ADDR (addr, IA64_LOC_TYPE_FP);
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default:
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return IA64_REG_LOC (c, reg);
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}
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}
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else if (c->last_abi_marker == ABI_MARKER_OLD_LINUX_INTERRUPT)
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{
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switch (reg)
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{
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case UNW_IA64_GR + 1 ... UNW_IA64_GR + 3:
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addr += LINUX_OLD_PT_R1_OFF + 8 * (reg - (UNW_IA64_GR + 1));
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break;
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case UNW_IA64_GR + 8 ... UNW_IA64_GR + 11:
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addr += LINUX_OLD_PT_R8_OFF + 8 * (reg - (UNW_IA64_GR + 8));
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break;
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case UNW_IA64_GR + 16 ... UNW_IA64_GR + 31:
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addr += LINUX_OLD_PT_R16_OFF + 8 * (reg - (UNW_IA64_GR + 16));
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break;
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case UNW_IA64_FR + 6 ... UNW_IA64_FR + 9:
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addr += LINUX_OLD_PT_F6_OFF + 16 * (reg - (UNW_IA64_FR + 6));
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return IA64_LOC_ADDR (addr, IA64_LOC_TYPE_FP);
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case UNW_IA64_BR + 0: addr += LINUX_OLD_PT_B0_OFF; break;
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case UNW_IA64_BR + 6: addr += LINUX_OLD_PT_B6_OFF; break;
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case UNW_IA64_BR + 7: addr += LINUX_OLD_PT_B7_OFF; break;
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case UNW_IA64_AR_RSC: addr += LINUX_OLD_PT_RSC_OFF; break;
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case UNW_IA64_AR_CCV: addr += LINUX_OLD_PT_CCV_OFF; break;
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default:
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return IA64_REG_LOC (c, reg);
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}
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}
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if (is_nat)
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{
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/* For Linux pt-regs structure, bit number is determined by
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the UNaT slot number (as determined by st8.spill) and the
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bits are saved wherever the (primary) UNaT was saved. */
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*nat_bitnr = ia64_unat_slot_num (addr);
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return c->loc[IA64_REG_PRI_UNAT_MEM];
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}
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return IA64_LOC_ADDR (addr, 0);
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}
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#endif
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return IA64_NULL_LOC;
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}
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static inline ia64_loc_t
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hpux_scratch_loc (struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr)
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{
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#if !defined(UNW_LOCAL_ONLY) || defined(__hpux)
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return IA64_LOC_UC_REG (reg, c->sigcontext_addr);
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#else
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return IA64_NULL_LOC;
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#endif
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}
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HIDDEN ia64_loc_t
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ia64_scratch_loc (struct cursor *c, unw_regnum_t reg, uint8_t *nat_bitnr)
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{
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if (c->sigcontext_addr)
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{
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if (c->as->abi == ABI_LINUX)
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return linux_scratch_loc (c, reg, nat_bitnr);
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else if (c->as->abi == ABI_HPUX)
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return hpux_scratch_loc (c, reg, nat_bitnr);
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else
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return IA64_NULL_LOC;
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}
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else
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return IA64_REG_LOC (c, reg);
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}
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static inline int
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update_nat (struct cursor *c, ia64_loc_t nat_loc, unw_word_t mask,
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unw_word_t *valp, int write)
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{
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unw_word_t nat_word;
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int ret;
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ret = ia64_get (c, nat_loc, &nat_word);
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if (ret < 0)
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return ret;
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if (write)
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{
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if (*valp)
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nat_word |= mask;
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else
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nat_word &= ~mask;
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ret = ia64_put (c, nat_loc, nat_word);
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}
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else
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*valp = (nat_word & mask) != 0;
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return ret;
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}
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static int
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access_nat (struct cursor *c,
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ia64_loc_t nat_loc, ia64_loc_t reg_loc, uint8_t nat_bitnr,
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unw_word_t *valp, int write)
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{
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unw_word_t mask = 0;
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unw_fpreg_t tmp;
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int ret;
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if (IA64_IS_FP_LOC (reg_loc))
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{
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/* NaT bit is saved as a NaTVal. This happens when a general
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register is saved to a floating-point register. */
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if (write)
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{
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if (*valp)
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{
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if (c->as->big_endian)
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ret = ia64_putfp (c, reg_loc, unw.nat_val_be);
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else
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ret = ia64_putfp (c, reg_loc, unw.nat_val_le);
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}
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else
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{
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unw_fpreg_t tmp;
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ret = ia64_getfp (c, reg_loc, &tmp);
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if (ret < 0)
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return ret;
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/* Reset the exponent to 0x1003e so that the significand
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will be interpreted as an integer value. */
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if (c->as->big_endian)
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tmp.raw.bits[0] = unw.int_val_be.raw.bits[0];
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else
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tmp.raw.bits[1] = unw.int_val_le.raw.bits[1];
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ret = ia64_putfp (c, reg_loc, tmp);
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}
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}
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else
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{
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ret = ia64_getfp (c, reg_loc, &tmp);
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if (ret < 0)
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return ret;
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if (c->as->big_endian)
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*valp = (memcmp (&tmp, &unw.nat_val_be, sizeof (tmp)) == 0);
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else
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*valp = (memcmp (&tmp, &unw.nat_val_le, sizeof (tmp)) == 0);
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}
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return ret;
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}
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if ((IA64_IS_REG_LOC (nat_loc)
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&& (unsigned) (IA64_GET_REG (nat_loc) - UNW_IA64_NAT) < 128)
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|| IA64_IS_UC_LOC (reg_loc))
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{
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if (write)
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return ia64_put (c, nat_loc, *valp);
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else
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return ia64_get (c, nat_loc, valp);
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}
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if (IA64_IS_NULL_LOC (nat_loc))
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{
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/* NaT bit is not saved. This happens if a general register is
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saved to a branch register. Since the NaT bit gets lost, we
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need to drop it here, too. Note that if the NaT bit had been
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set when the save occurred, it would have caused a NaT
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consumption fault. */
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if (write)
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{
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if (*valp)
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return -UNW_EBADREG; /* can't set NaT bit */
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}
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else
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*valp = 0;
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return 0;
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}
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mask = (unw_word_t) 1 << nat_bitnr;
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return update_nat (c, nat_loc, mask, valp, write);
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}
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HIDDEN int
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tdep_access_reg (struct cursor *c, unw_regnum_t reg, unw_word_t *valp,
|
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int write)
|
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{
|
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ia64_loc_t loc, reg_loc, nat_loc;
|
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unw_word_t nat, mask, pr;
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int ret, readonly = 0;
|
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uint8_t nat_bitnr;
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switch (reg)
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{
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/* frame registers: */
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case UNW_IA64_BSP:
|
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if (write)
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return -UNW_EREADONLYREG;
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*valp = c->bsp;
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return 0;
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case UNW_REG_SP:
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if (write)
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return -UNW_EREADONLYREG;
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*valp = c->sp;
|
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return 0;
|
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case UNW_REG_IP:
|
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if (write)
|
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{
|
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c->ip = *valp; /* also update the IP cache */
|
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if (c->pi_valid && (*valp < c->pi.start_ip || *valp >= c->pi.end_ip))
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c->pi_valid = 0; /* new IP outside of current proc */
|
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}
|
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loc = c->loc[IA64_REG_IP];
|
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break;
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|
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/* preserved registers: */
|
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|
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case UNW_IA64_GR + 4 ... UNW_IA64_GR + 7:
|
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loc = c->loc[IA64_REG_R4 + (reg - (UNW_IA64_GR + 4))];
|
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break;
|
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|
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case UNW_IA64_NAT + 4 ... UNW_IA64_NAT + 7:
|
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loc = c->loc[IA64_REG_NAT4 + (reg - (UNW_IA64_NAT + 4))];
|
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reg_loc = c->loc[IA64_REG_R4 + (reg - (UNW_IA64_NAT + 4))];
|
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nat_bitnr = c->nat_bitnr[reg - (UNW_IA64_NAT + 4)];
|
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return access_nat (c, loc, reg_loc, nat_bitnr, valp, write);
|
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|
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case UNW_IA64_AR_BSP: loc = c->loc[IA64_REG_BSP]; break;
|
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case UNW_IA64_AR_BSPSTORE: loc = c->loc[IA64_REG_BSPSTORE]; break;
|
||||
case UNW_IA64_AR_PFS: loc = c->loc[IA64_REG_PFS]; break;
|
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case UNW_IA64_AR_RNAT: loc = c->loc[IA64_REG_RNAT]; break;
|
||||
case UNW_IA64_AR_UNAT: loc = c->loc[IA64_REG_UNAT]; break;
|
||||
case UNW_IA64_AR_LC: loc = c->loc[IA64_REG_LC]; break;
|
||||
case UNW_IA64_AR_FPSR: loc = c->loc[IA64_REG_FPSR]; break;
|
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case UNW_IA64_BR + 1: loc = c->loc[IA64_REG_B1]; break;
|
||||
case UNW_IA64_BR + 2: loc = c->loc[IA64_REG_B2]; break;
|
||||
case UNW_IA64_BR + 3: loc = c->loc[IA64_REG_B3]; break;
|
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case UNW_IA64_BR + 4: loc = c->loc[IA64_REG_B4]; break;
|
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case UNW_IA64_BR + 5: loc = c->loc[IA64_REG_B5]; break;
|
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|
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case UNW_IA64_CFM:
|
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if (write)
|
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c->cfm = *valp; /* also update the CFM cache */
|
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loc = c->cfm_loc;
|
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break;
|
||||
|
||||
case UNW_IA64_PR:
|
||||
if (write)
|
||||
{
|
||||
c->pr = *valp; /* update the predicate cache */
|
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pr = pr_ltop (c, *valp);
|
||||
return ia64_put (c, c->loc[IA64_REG_PR], pr);
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = ia64_get (c, c->loc[IA64_REG_PR], &pr);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
*valp = pr_ptol (c, pr);
|
||||
}
|
||||
return 0;
|
||||
|
||||
case UNW_IA64_GR + 32 ... UNW_IA64_GR + 127: /* stacked reg */
|
||||
reg = rotate_gr (c, reg - UNW_IA64_GR);
|
||||
if (reg < 0)
|
||||
return -UNW_EBADREG;
|
||||
ret = ia64_get_stacked (c, reg, &loc, NULL);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
break;
|
||||
|
||||
case UNW_IA64_NAT + 32 ... UNW_IA64_NAT + 127: /* stacked reg */
|
||||
reg = rotate_gr (c, reg - UNW_IA64_NAT);
|
||||
if (reg < 0)
|
||||
return -UNW_EBADREG;
|
||||
ret = ia64_get_stacked (c, reg, &loc, &nat_loc);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
assert (!IA64_IS_REG_LOC (loc));
|
||||
mask = (unw_word_t) 1 << ia64_rse_slot_num (IA64_GET_ADDR (loc));
|
||||
return update_nat (c, nat_loc, mask, valp, write);
|
||||
|
||||
case UNW_IA64_AR_EC:
|
||||
if (write)
|
||||
{
|
||||
c->cfm = ((c->cfm & ~((unw_word_t) 0x3f << 52))
|
||||
| ((*valp & 0x3f) << 52));
|
||||
return ia64_put (c, c->cfm_loc, c->cfm);
|
||||
}
|
||||
else
|
||||
{
|
||||
*valp = (c->cfm >> 52) & 0x3f;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* scratch & special registers: */
|
||||
|
||||
case UNW_IA64_GR + 0:
|
||||
if (write)
|
||||
return -UNW_EREADONLYREG;
|
||||
*valp = 0;
|
||||
return 0;
|
||||
|
||||
case UNW_IA64_GR + 1: /* global pointer */
|
||||
if (write)
|
||||
return -UNW_EREADONLYREG;
|
||||
|
||||
/* ensure c->pi is up-to-date: */
|
||||
if ((ret = ia64_make_proc_info (c)) < 0)
|
||||
return ret;
|
||||
*valp = c->pi.gp;
|
||||
return 0;
|
||||
|
||||
case UNW_IA64_NAT + 0:
|
||||
case UNW_IA64_NAT + 1: /* global pointer */
|
||||
if (write)
|
||||
return -UNW_EREADONLYREG;
|
||||
*valp = 0;
|
||||
return 0;
|
||||
|
||||
case UNW_IA64_NAT + 2 ... UNW_IA64_NAT + 3:
|
||||
case UNW_IA64_NAT + 8 ... UNW_IA64_NAT + 31:
|
||||
loc = ia64_scratch_loc (c, reg, &nat_bitnr);
|
||||
if (!(IA64_IS_REG_LOC (loc) || IA64_IS_UC_LOC (loc)
|
||||
|| IA64_IS_FP_LOC (loc)))
|
||||
{
|
||||
/* We're dealing with a NaT bit stored in memory. */
|
||||
mask = (unw_word_t) 1 << nat_bitnr;
|
||||
|
||||
if ((ret = ia64_get (c, loc, &nat)) < 0)
|
||||
return ret;
|
||||
|
||||
if (write)
|
||||
{
|
||||
if (*valp)
|
||||
nat |= mask;
|
||||
else
|
||||
nat &= ~mask;
|
||||
ret = ia64_put (c, loc, nat);
|
||||
}
|
||||
else
|
||||
*valp = (nat & mask) != 0;
|
||||
return ret;
|
||||
}
|
||||
break;
|
||||
|
||||
case UNW_IA64_GR + 15 ... UNW_IA64_GR + 18:
|
||||
mask = 1 << (reg - (UNW_IA64_GR + 15));
|
||||
if (write)
|
||||
{
|
||||
c->eh_args[reg - (UNW_IA64_GR + 15)] = *valp;
|
||||
c->eh_valid_mask |= mask;
|
||||
return 0;
|
||||
}
|
||||
else if ((c->eh_valid_mask & mask) != 0)
|
||||
{
|
||||
*valp = c->eh_args[reg - (UNW_IA64_GR + 15)] = *valp;
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
loc = ia64_scratch_loc (c, reg, NULL);
|
||||
break;
|
||||
|
||||
case UNW_IA64_GR + 2 ... UNW_IA64_GR + 3:
|
||||
case UNW_IA64_GR + 8 ... UNW_IA64_GR + 14:
|
||||
case UNW_IA64_GR + 19 ... UNW_IA64_GR + 31:
|
||||
case UNW_IA64_BR + 0:
|
||||
case UNW_IA64_BR + 6:
|
||||
case UNW_IA64_BR + 7:
|
||||
case UNW_IA64_AR_RSC:
|
||||
case UNW_IA64_AR_CSD:
|
||||
case UNW_IA64_AR_SSD:
|
||||
case UNW_IA64_AR_CCV:
|
||||
loc = ia64_scratch_loc (c, reg, NULL);
|
||||
break;
|
||||
|
||||
default:
|
||||
Debug (1, "bad register number %d\n", reg);
|
||||
return -UNW_EBADREG;
|
||||
}
|
||||
|
||||
if (write)
|
||||
{
|
||||
if (readonly)
|
||||
return -UNW_EREADONLYREG;
|
||||
return ia64_put (c, loc, *valp);
|
||||
}
|
||||
else
|
||||
return ia64_get (c, loc, valp);
|
||||
}
|
||||
|
||||
HIDDEN int
|
||||
tdep_access_fpreg (struct cursor *c, int reg, unw_fpreg_t *valp,
|
||||
int write)
|
||||
{
|
||||
ia64_loc_t loc;
|
||||
|
||||
switch (reg)
|
||||
{
|
||||
case UNW_IA64_FR + 0:
|
||||
if (write)
|
||||
return -UNW_EREADONLYREG;
|
||||
*valp = unw.read_only.f0;
|
||||
return 0;
|
||||
|
||||
case UNW_IA64_FR + 1:
|
||||
if (write)
|
||||
return -UNW_EREADONLYREG;
|
||||
|
||||
if (c->as->big_endian)
|
||||
*valp = unw.read_only.f1_be;
|
||||
else
|
||||
*valp = unw.read_only.f1_le;
|
||||
return 0;
|
||||
|
||||
case UNW_IA64_FR + 2: loc = c->loc[IA64_REG_F2]; break;
|
||||
case UNW_IA64_FR + 3: loc = c->loc[IA64_REG_F3]; break;
|
||||
case UNW_IA64_FR + 4: loc = c->loc[IA64_REG_F4]; break;
|
||||
case UNW_IA64_FR + 5: loc = c->loc[IA64_REG_F5]; break;
|
||||
|
||||
case UNW_IA64_FR + 16 ... UNW_IA64_FR + 31:
|
||||
loc = c->loc[IA64_REG_F16 + (reg - (UNW_IA64_FR + 16))];
|
||||
break;
|
||||
|
||||
case UNW_IA64_FR + 6 ... UNW_IA64_FR + 15:
|
||||
loc = ia64_scratch_loc (c, reg, NULL);
|
||||
break;
|
||||
|
||||
case UNW_IA64_FR + 32 ... UNW_IA64_FR + 127:
|
||||
reg = rotate_fr (c, reg - UNW_IA64_FR) + UNW_IA64_FR;
|
||||
loc = ia64_scratch_loc (c, reg, NULL);
|
||||
break;
|
||||
|
||||
default:
|
||||
Debug (1, "bad register number %d\n", reg);
|
||||
return -UNW_EBADREG;
|
||||
}
|
||||
|
||||
if (write)
|
||||
return ia64_putfp (c, loc, *valp);
|
||||
else
|
||||
return ia64_getfp (c, loc, valp);
|
||||
}
|
||||
Loading…
Reference in a new issue