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Rename: src/ia64/Grbs-ia64.c -> src/ia64/Grbs.c
}(Logical change 1.241)
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/* libunwind - a platform-independent unwind library
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Copyright (C) 2003-2004 Hewlett-Packard Co
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
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This file is part of libunwind.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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/* Logically, we like to think of the stack as a contiguous region of
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memory. Unfortunately, this logical view doesn't work for the
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register backing store, because the RSE is an asynchronous engine and
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because UNIX/Linux allow for stack-switching via sigaltstack(2).
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Specifically, this means that any given stacked register may or may
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not be backed up by memory in the current stack. If not, then the
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backing memory may be found in any of the "more inner" (younger)
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stacks. The routines in this file help manage the discontiguous
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nature of the register backing store. The routines are completely
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independent of UNIX/Linux, but each stack frame that switches the
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backing store is expected to reserve 4 words for use by libunwind. For
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example, in the Linux sigcontext, sc_fr[0] and sc_fr[1] serve this
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purpose. */
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#include "unwind_i.h"
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HIDDEN int
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rbs_switch (struct cursor *c,
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unw_word_t saved_bsp, unw_word_t saved_bspstore,
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ia64_loc_t saved_rnat_loc)
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{
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struct rbs_area *rbs = &c->rbs_area[c->rbs_curr];
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unw_word_t lo, ndirty;
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Debug (10, "(left=%u, curr=%u)", c->rbs_left_edge, c->rbs_curr);
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/* Calculate address "lo" at which the backing store starts: */
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ndirty = ia64_rse_num_regs (saved_bspstore, saved_bsp);
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lo = ia64_rse_skip_regs (c->bsp, -ndirty);
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rbs->size = (rbs->end - lo);
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/* If the previously-recorded rbs-area is empty we don't need to
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track it and we can simply overwrite it... */
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if (rbs->size)
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{
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Debug (10, "inner=[0x%lx-0x%lx)",
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(long) (rbs->end - rbs->size), (long) rbs->end);
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c->rbs_curr = (c->rbs_curr + 1) % NELEMS (c->rbs_area);
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rbs = c->rbs_area + c->rbs_curr;
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if (c->rbs_curr == c->rbs_left_edge)
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c->rbs_left_edge = (c->rbs_left_edge + 1) % NELEMS (c->rbs_area);
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}
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rbs->end = saved_bspstore;
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rbs->size = ((unw_word_t) 1) << 63; /* initial guess... */
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rbs->rnat_loc = saved_rnat_loc;
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c->bsp = saved_bsp;
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Debug (10, "outer=[?????????????????\?-0x%llx), rnat@%s\n",
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(long long) rbs->end, ia64_strloc (rbs->rnat_loc));
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return 0;
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}
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HIDDEN int
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rbs_find_stacked (struct cursor *c, unw_word_t regs_to_skip,
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ia64_loc_t *locp, ia64_loc_t *rnat_locp)
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{
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unw_word_t nregs, bsp = c->bsp, curr = c->rbs_curr, n;
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unw_word_t left_edge = c->rbs_left_edge;
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#if UNW_DEBUG
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int reg = 32 + regs_to_skip;
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#endif
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while (!rbs_contains (&c->rbs_area[curr], bsp))
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{
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if (curr == left_edge)
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{
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Debug (1, "could not find register r%d!\n", reg);
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return -UNW_EBADREG;
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}
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n = ia64_rse_num_regs (c->rbs_area[curr].end, bsp);
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curr = (curr + NELEMS (c->rbs_area) - 1) % NELEMS (c->rbs_area);
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bsp = ia64_rse_skip_regs (c->rbs_area[curr].end - c->rbs_area[curr].size,
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n);
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}
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while (1)
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{
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nregs = ia64_rse_num_regs (bsp, c->rbs_area[curr].end);
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if (regs_to_skip < nregs)
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{
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/* found it: */
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unw_word_t addr;
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addr = ia64_rse_skip_regs (bsp, regs_to_skip);
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if (locp)
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*locp = rbs_loc (c->rbs_area + curr, addr);
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if (rnat_locp)
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*rnat_locp = rbs_get_rnat_loc (c->rbs_area + curr, addr);
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return 0;
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}
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if (curr == left_edge)
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{
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Debug (1, "could not find register r%d!\n", reg);
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return -UNW_EBADREG;
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}
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regs_to_skip -= nregs;
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curr = (curr + NELEMS (c->rbs_area) - 1) % NELEMS (c->rbs_area);
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bsp = c->rbs_area[curr].end - c->rbs_area[curr].size;
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}
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}
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static inline int
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get_rnat (struct cursor *c, struct rbs_area *rbs, unw_word_t bsp,
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ia64_loc_t *__restrict rnat_locp, unw_word_t *__restrict rnatp)
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{
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*rnat_locp = rbs_get_rnat_loc (rbs, bsp);
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return ia64_get (c, *rnat_locp, rnatp);
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}
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/* Ensure that the first "nregs" stacked registers are on the current
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register backing store area. This effectively simulates the effect
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of a "cover" followed by a "flushrs" for the current frame.
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Note: This does not modify the rbs_area[] structure in any way. */
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HIDDEN int
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rbs_cover_and_flush (struct cursor *c, unw_word_t nregs)
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{
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unw_word_t src_mask, dst_mask, curr, val, left_edge = c->rbs_left_edge;
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unw_word_t src_bsp, dst_bsp, src_rnat, dst_rnat, dst_rnat_addr;
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ia64_loc_t src_rnat_loc, dst_rnat_loc;
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unw_word_t final_bsp;
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struct rbs_area *dst_rbs;
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int ret;
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if (nregs < 1)
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return 0; /* nothing to do... */
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/* Handle the common case quickly: */
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curr = c->rbs_curr;
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dst_rbs = c->rbs_area + curr;
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final_bsp = ia64_rse_skip_regs (c->bsp, nregs); /* final bsp */
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if (likely (rbs_contains (dst_rbs, final_bsp) || curr == left_edge))
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{
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dst_rnat_addr = ia64_rse_rnat_addr (ia64_rse_skip_regs (c->bsp,
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nregs - 1));
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if (rbs_contains (dst_rbs, dst_rnat_addr))
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c->loc[IA64_REG_RNAT] = rbs_loc (dst_rbs, dst_rnat_addr);
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c->bsp = final_bsp;
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return 0;
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}
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/* Skip over regs that are already on the destination rbs-area: */
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dst_bsp = src_bsp = dst_rbs->end;
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if ((ret = get_rnat (c, dst_rbs, dst_bsp, &dst_rnat_loc, &dst_rnat)) < 0)
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return ret;
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/* This may seem a bit surprising, but with a hyper-lazy RSE, it's
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perfectly common that ar.bspstore points to an RNaT slot at the
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time of a backing-store switch. When that happens, install the
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appropriate RNaT value (if necessary) and move on to the next
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slot. */
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if (ia64_rse_is_rnat_slot (dst_bsp))
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{
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if ((IA64_IS_REG_LOC (dst_rnat_loc)
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|| IA64_GET_ADDR (dst_rnat_loc) != dst_bsp)
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&& (ret = ia64_put (c, rbs_loc (dst_rbs, dst_bsp), dst_rnat)) < 0)
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return ret;
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dst_bsp = src_bsp = dst_bsp + 8;
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}
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while (dst_bsp != final_bsp)
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{
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while (!rbs_contains (&c->rbs_area[curr], src_bsp))
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{
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/* switch to next rbs-area, adjust src_bsp accordingly: */
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if (curr == left_edge)
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{
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Debug (1, "rbs-underflow while flushing %lu regs, "
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"src_bsp=0x%lx, dst_bsp=0x%lx\n", (unsigned long) nregs,
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(unsigned long) src_bsp, (unsigned long) dst_bsp);
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return -UNW_EBADREG;
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}
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curr = (curr + NELEMS (c->rbs_area) - 1) % NELEMS (c->rbs_area);
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src_bsp = c->rbs_area[curr].end - c->rbs_area[curr].size;
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}
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/* OK, found the right rbs-area. Now copy both the register
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value and its NaT bit: */
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if ((ret = get_rnat (c, c->rbs_area + curr, src_bsp,
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&src_rnat_loc, &src_rnat)) < 0)
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return ret;
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src_mask = ((unw_word_t) 1) << ia64_rse_slot_num (src_bsp);
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dst_mask = ((unw_word_t) 1) << ia64_rse_slot_num (dst_bsp);
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if (src_rnat & src_mask)
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dst_rnat |= dst_mask;
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else
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dst_rnat &= ~dst_mask;
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if ((ret = ia64_get (c, rbs_loc (c->rbs_area + curr, src_bsp), &val)) < 0
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|| (ret = ia64_put (c, rbs_loc (dst_rbs, dst_bsp), val)) < 0)
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return ret;
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/* advance src_bsp & dst_bsp to next slot: */
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src_bsp += 8;
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if (ia64_rse_is_rnat_slot (src_bsp))
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src_bsp += 8;
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dst_bsp += 8;
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if (ia64_rse_is_rnat_slot (dst_bsp))
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{
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if ((ret = ia64_put (c, rbs_loc (dst_rbs, dst_bsp), dst_rnat)) < 0)
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return ret;
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dst_bsp += 8;
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if ((ret = get_rnat (c, dst_rbs, dst_bsp,
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&dst_rnat_loc, &dst_rnat)) < 0)
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return ret;
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}
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}
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c->bsp = dst_bsp;
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c->loc[IA64_REG_RNAT] = dst_rnat_loc;
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return ia64_put (c, dst_rnat_loc, dst_rnat);
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}
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