mirror of
https://github.com/tobast/libunwind-eh_elf.git
synced 2024-11-22 07:37:38 +01:00
Include "offsets.h" to get offsets for various structures (such
as sigcontext). Adjust for the fact that the RSE arithmetic is now done on values of type unw_word_t rather than long pointers. (ia64_scratch_loc): Rename from ia64_get_sigcontext() and expand it such that it returns a scratch register location if the current frame is not a sigcontext frame. (ia64_access_reg): Read the address of the personality routine with ia64_get() rather than trying to dereference the address directly. When writing the IP or the PR, update the cached values, too. (Logical change 1.5)
This commit is contained in:
(none)!davidm
parent
3790561497
commit
7820abd977
1 changed files with 153 additions and 145 deletions
298
src/ia64/regs.c
298
src/ia64/regs.c
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@ -21,29 +21,54 @@ This exception does not however invalidate any other reasons why the
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executable file might be covered by the GNU General Public
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License. */
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#include "config.h"
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#include <assert.h>
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#include "unwind_i.h"
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#include "rse.h"
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/* The first three 64-bit words in a signal frame contain the signal
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number, siginfo pointer, and sigcontext pointer passed to the
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signal handler. We use this to locate the sigcontext pointer. */
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#define SIGFRAME_ARG2_OFF 0x10
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#include "offsets.h"
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#include "rse.h"
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#include "unwind_i.h"
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unw_word_t
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ia64_get_sigcontext_addr (struct ia64_cursor *c)
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ia64_scratch_loc (struct ia64_cursor *c, unw_regnum_t reg)
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{
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unw_word_t addr;
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unw_word_t loc;
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if (!(c->pi.flags & IA64_FLAG_SIGTRAMP))
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return 0;
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if (c->pi.flags & IA64_FLAG_SIGTRAMP)
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{
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if (ia64_get (c, c->sp + 0x10 + SIGFRAME_ARG2_OFF, &loc) < 0)
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return 0;
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if (ia64_get (c, c->sp + 0x10 + SIGFRAME_ARG2_OFF, &addr) < 0)
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return 0;
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switch (reg)
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{
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case UNW_IA64_NAT + 2 ... UNW_IA64_NAT + 3:
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case UNW_IA64_NAT + 8 ... UNW_IA64_NAT + 31:
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loc += SIGCONTEXT_NAT_OFF;
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break;
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return addr;
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case UNW_IA64_GR + 2 ... UNW_IA64_GR + 3:
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case UNW_IA64_GR + 8 ... UNW_IA64_GR + 31:
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loc += SIGCONTEXT_GR_OFF + 8*reg;
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break;
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case UNW_IA64_FR + 6 ... UNW_IA64_FR + 15:
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loc += SIGCONTEXT_FR_OFF + 16*(reg - UNW_IA64_FR);
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break;
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case UNW_IA64_FR + 32 ... UNW_IA64_FR + 127:
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loc += SIGCONTEXT_FR_OFF + 16*(reg - UNW_IA64_FR);
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break;
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case UNW_IA64_BR + 0: loc += SIGCONTEXT_BR_OFF + 0; break;
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case UNW_IA64_BR + 7: loc += SIGCONTEXT_BR_OFF + 7*8; break;
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case UNW_IA64_AR_RSC: loc += SIGCONTEXT_AR_RSC_OFF; break;
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case UNW_IA64_AR_25: loc += SIGCONTEXT_AR_25_OFF; break;
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case UNW_IA64_AR_26: loc += SIGCONTEXT_AR_26_OFF; break;
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case UNW_IA64_AR_CCV: loc += SIGCONTEXT_AR_CCV; break;
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}
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return loc;
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}
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else
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return IA64_REG_LOC (reg);
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}
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/* Apply rotation to a general register. The number REG must be in
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@ -171,7 +196,7 @@ access_nat (struct ia64_cursor *c, unw_word_t loc, unw_word_t reg_loc,
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{
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unw_word_t nat_loc = -8, mask = 0, sc_addr;
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unw_fpreg_t tmp;
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int ret;
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int ret, reg;
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if (IA64_IS_FP_LOC (reg_loc))
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{
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@ -221,13 +246,13 @@ access_nat (struct ia64_cursor *c, unw_word_t loc, unw_word_t reg_loc,
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if (IA64_IS_MEMSTK_NAT (loc))
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{
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nat_loc = IA64_GET_LOC (loc) << 3;
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mask = (unw_word_t) 1 << ia64_rse_slot_num ((unsigned long *) reg_loc);
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mask = (unw_word_t) 1 << ia64_rse_slot_num (reg_loc);
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}
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else
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{
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loc = IA64_GET_LOC (loc);
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assert (loc >= 0 && loc < 128);
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if (!loc)
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reg = IA64_GET_LOC (loc);
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assert (reg >= 0 && reg < 128);
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if (!reg)
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{
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/* NaT bit is not saved. This happens if a general register
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is saved to a branch register. Since the NaT bit gets
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@ -244,39 +269,44 @@ access_nat (struct ia64_cursor *c, unw_word_t loc, unw_word_t reg_loc,
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return 0;
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}
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if (loc >= 4 && loc <= 7)
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if (reg >= 4 && reg <= 7)
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{
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/* NaT bit is saved in a NaT register. This happens when a
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general register is saved to another general
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register. */
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if (write)
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ret = ia64_put (c, UNW_IA64_NAT + loc, *valp);
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ret = ia64_put (c, UNW_IA64_NAT + reg, *valp);
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else
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ret = ia64_get (c, UNW_IA64_NAT + loc, valp);
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ret = ia64_get (c, UNW_IA64_NAT + reg, valp);
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return ret;
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}
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else if (loc >= 32)
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else if (reg >= 32)
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{
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/* NaT bit is saved in a stacked register. */
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nat_loc = (unw_word_t) ia64_rse_rnat_addr ((unsigned long *)
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reg_loc);
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nat_loc = (intptr_t) ia64_rse_rnat_addr (reg_loc);
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if (nat_loc > c->rbs_top)
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nat_loc = c->top_rnat_loc;
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mask = (unw_word_t) 1 << ia64_rse_slot_num ((unsigned long *)
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reg_loc);
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mask = (intptr_t) 1 << ia64_rse_slot_num (reg_loc);
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}
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else
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{
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/* NaT bit is saved in a scratch register. */
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if (!(c->pi.flags & IA64_FLAG_SIGTRAMP))
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return -UNW_EBADREG;
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if (c->pi.flags & IA64_FLAG_SIGTRAMP)
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{
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ret = ia64_get (c, c->sp + 0x10 + SIGFRAME_ARG2_OFF, &sc_addr);
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if (ret < 0)
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return ret;
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sc_addr = ia64_get_sigcontext_addr (c);
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if (!sc_addr)
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return -UNW_EBADREG;
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nat_loc = sc_addr + struct_offset (struct sigcontext, sc_nat);
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mask = (unw_word_t) 1 << loc;
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nat_loc = sc_addr + SIGCONTEXT_NAT_OFF;
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mask = (unw_word_t) 1 << reg;
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}
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else
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{
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if (write)
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return ia64_put (c, loc, *valp);
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else
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return ia64_get (c, loc, valp);
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}
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}
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}
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return update_nat (c, nat_loc, mask, valp, write);
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@ -286,7 +316,7 @@ int
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ia64_access_reg (struct ia64_cursor *c, unw_regnum_t reg, unw_word_t *valp,
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int write)
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{
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unw_word_t loc = -8, reg_loc, sc_off = 0, nat, nat_loc, cfm, mask, pr;
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unw_word_t loc = -8, reg_loc, nat, nat_loc, cfm, mask, pr;
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int ret, readonly = 0;
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switch (reg)
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@ -310,14 +340,14 @@ ia64_access_reg (struct ia64_cursor *c, unw_regnum_t reg, unw_word_t *valp,
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case UNW_REG_SP: *valp = c->sp; break;
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case UNW_REG_PROC_START:*valp = c->pi.proc_start; break;
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case UNW_REG_LSDA:
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*valp = (unw_word_t) (c->pi.pers_addr + 1);
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*valp = (intptr_t) (c->pi.pers_addr + 1);
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break;
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case UNW_REG_HANDLER:
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if (c->pi.flags & IA64_FLAG_HAS_HANDLER)
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/* *c->pers_addr is the linkage-table offset of the word
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that stores the address of the personality routine's
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function descriptor. */
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*valp = *(unw_word_t *) (*c->pi.pers_addr + c->pi.gp);
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return ia64_get (c, *c->pi.pers_addr + c->pi.gp, valp);
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else
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*valp = 0;
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break;
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@ -325,15 +355,23 @@ ia64_access_reg (struct ia64_cursor *c, unw_regnum_t reg, unw_word_t *valp,
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return 0;
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case UNW_REG_IP:
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loc = c->rp_loc;
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if (write)
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c->ip = *valp; /* also update the IP cache */
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loc = c->ip_loc;
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break;
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/* preserved registers: */
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case UNW_IA64_GR + 4: loc = c->r4_loc; break;
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case UNW_IA64_GR + 5: loc = c->r5_loc; break;
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case UNW_IA64_GR + 6: loc = c->r6_loc; break;
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case UNW_IA64_GR + 7: loc = c->r7_loc; break;
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case UNW_IA64_GR + 4 ... UNW_IA64_GR + 7:
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loc = (&c->r4_loc)[reg - (UNW_IA64_GR + 4)];
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break;
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case UNW_IA64_NAT + 4 ... UNW_IA64_NAT + 7:
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loc = (&c->nat4_loc)[reg - (UNW_IA64_NAT + 4)];
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reg_loc = (&c->r4_loc)[reg - (UNW_IA64_NAT + 4)];
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return access_nat (c, loc, reg_loc, valp, write);
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case UNW_IA64_AR_BSP: loc = c->bsp_loc; break;
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case UNW_IA64_AR_BSPSTORE: loc = c->bspstore_loc; break;
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case UNW_IA64_AR_PFS: loc = c->pfs_loc; break;
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@ -351,6 +389,7 @@ ia64_access_reg (struct ia64_cursor *c, unw_regnum_t reg, unw_word_t *valp,
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case UNW_IA64_PR:
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if (write)
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{
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c->pr = *valp; /* update the predicate cache */
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pr = pr_ltop (c, *valp);
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return ia64_put (c, c->pr_loc, pr);
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}
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@ -365,18 +404,16 @@ ia64_access_reg (struct ia64_cursor *c, unw_regnum_t reg, unw_word_t *valp,
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case UNW_IA64_GR + 32 ... UNW_IA64_GR + 127: /* stacked reg */
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reg = rotate_gr (c, reg - UNW_IA64_GR) + UNW_IA64_GR;
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loc = (unw_word_t) ia64_rse_skip_regs ((unsigned long *) c->bsp,
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reg - (UNW_IA64_GR + 32));
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loc = ia64_rse_skip_regs (c->bsp, reg - (UNW_IA64_GR + 32));
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break;
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case UNW_IA64_NAT + 32 ... UNW_IA64_NAT + 127: /* stacked reg */
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reg = rotate_gr (c, reg - UNW_IA64_NAT) + UNW_IA64_NAT;
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loc = (unw_word_t) ia64_rse_skip_regs ((unsigned long *) c->bsp,
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reg - (UNW_IA64_NAT + 32));
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nat_loc = (unw_word_t) ia64_rse_rnat_addr ((unsigned long *) loc);
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loc = ia64_rse_skip_regs (c->bsp, reg - (UNW_IA64_NAT + 32));
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nat_loc = ia64_rse_rnat_addr (loc);
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if (nat_loc > c->rbs_top)
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nat_loc = c->top_rnat_loc;
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mask = (unw_word_t) 1 << ia64_rse_slot_num ((unsigned long *) loc);
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mask = (unw_word_t) 1 << ia64_rse_slot_num (loc);
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return update_nat (c, nat_loc, mask, valp, write);
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case UNW_IA64_AR_EC:
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@ -405,25 +442,6 @@ ia64_access_reg (struct ia64_cursor *c, unw_regnum_t reg, unw_word_t *valp,
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*valp = c->pi.gp;
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return 0;
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case UNW_IA64_GR + 15 ... UNW_IA64_GR + 18:
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if (!(c->pi.flags & IA64_FLAG_SIGTRAMP))
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{
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if (write)
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c->eh_args[reg - (UNW_IA64_GR + 15)] = *valp;
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else
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*valp = c->eh_args[reg - (UNW_IA64_GR + 15)] = *valp;
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return 0;
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}
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else
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sc_off = struct_offset (struct sigcontext, sc_gr[reg]);
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break;
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case UNW_IA64_GR + 2 ... UNW_IA64_GR + 3:
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case UNW_IA64_GR + 8 ... UNW_IA64_GR + 14:
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case UNW_IA64_GR + 19 ... UNW_IA64_GR + 31:
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sc_off = struct_offset (struct sigcontext, sc_gr[reg]);
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break;
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case UNW_IA64_NAT + 0:
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case UNW_IA64_NAT + 1: /* global pointer */
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if (write)
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@ -433,50 +451,52 @@ ia64_access_reg (struct ia64_cursor *c, unw_regnum_t reg, unw_word_t *valp,
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case UNW_IA64_NAT + 2 ... UNW_IA64_NAT + 3:
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case UNW_IA64_NAT + 8 ... UNW_IA64_NAT + 31:
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mask = (unw_word_t) 1 << (reg - UNW_IA64_NAT);
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loc = ia64_get_sigcontext_addr (c);
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if (!loc)
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return -UNW_EBADREG;
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loc += struct_offset (struct sigcontext, sc_nat);
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ret = ia64_get (c, loc, &nat);
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if (ret < 0)
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return ret;
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if (write)
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loc = ia64_scratch_loc (c, reg);
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if (c->pi.flags & IA64_FLAG_SIGTRAMP)
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{
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if (*valp)
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nat |= mask;
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mask = (unw_word_t) 1 << (reg - UNW_IA64_NAT);
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ret = ia64_get (c, loc, &nat);
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if (ret < 0)
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return ret;
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if (write)
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{
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if (*valp)
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nat |= mask;
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else
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nat &= ~mask;
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ret = ia64_put (c, loc, nat);
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}
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else
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nat &= ~mask;
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ret = ia64_put (c, loc, nat);
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*valp = (nat & mask) != 0;
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return ret;
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}
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break;
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case UNW_IA64_GR + 15 ... UNW_IA64_GR + 18:
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if (c->pi.flags & IA64_FLAG_SIGTRAMP)
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loc = ia64_scratch_loc (c, reg);
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else
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*valp = (nat & mask) != 0;
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return ret;
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case UNW_IA64_NAT + 4 ... UNW_IA64_NAT + 7:
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loc = (&c->nat4_loc)[reg - (UNW_IA64_NAT + 4)];
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reg_loc = (&c->r4_loc)[reg - (UNW_IA64_NAT + 4)];
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return access_nat (c, loc, reg_loc, valp, write);
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{
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if (write)
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c->eh_args[reg - (UNW_IA64_GR + 15)] = *valp;
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else
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*valp = c->eh_args[reg - (UNW_IA64_GR + 15)] = *valp;
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return 0;
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}
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break;
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case UNW_IA64_GR + 2 ... UNW_IA64_GR + 3:
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case UNW_IA64_GR + 8 ... UNW_IA64_GR + 14:
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case UNW_IA64_GR + 19 ... UNW_IA64_GR + 31:
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case UNW_IA64_BR + 0:
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case UNW_IA64_BR + 7:
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case UNW_IA64_AR_RSC:
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sc_off = struct_offset (struct sigcontext, sc_ar_rsc);
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break;
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#ifdef SIGCONTEXT_HAS_AR25_AND_AR26
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case UNW_IA64_AR_25:
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sc_off = struct_offset (struct sigcontext, sc_ar25);
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break;
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case UNW_IA64_AR_26:
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sc_off = struct_offset (struct sigcontext, sc_ar26);
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break;
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#endif
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case UNW_IA64_AR_CCV:
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sc_off = struct_offset (struct sigcontext, sc_ar_ccv);
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loc = ia64_scratch_loc (c, reg);
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break;
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default:
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@ -484,15 +504,6 @@ ia64_access_reg (struct ia64_cursor *c, unw_regnum_t reg, unw_word_t *valp,
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return -UNW_EBADREG;
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}
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if (sc_off)
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{
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loc = ia64_get_sigcontext_addr (c);
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if (!loc)
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return -UNW_EBADREG;
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loc += sc_off;
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}
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if (write)
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{
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if (readonly)
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@ -537,49 +548,46 @@ ia64_access_fpreg (struct ia64_cursor *c, int reg, unw_fpreg_t *valp,
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break;
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case UNW_IA64_FR + 6 ... UNW_IA64_FR + 15:
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loc = ia64_get_sigcontext_addr (c);
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if (!loc)
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return -UNW_EBADREG;
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loc += struct_offset (struct sigcontext, sc_fr[reg - UNW_IA64_FR]);
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loc = ia64_scratch_loc (c, reg);
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break;
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case UNW_IA64_FR + 32 ... UNW_IA64_FR + 127:
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reg = rotate_fr (c, reg - UNW_IA64_FR) + UNW_IA64_FR;
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loc = ia64_get_sigcontext_addr (c);
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if (!loc)
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return -UNW_EBADREG;
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ret = ia64_get (c, loc + struct_offset (struct sigcontext, sc_flags),
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&flags);
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if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (!(flags & IA64_SC_FLAG_FPH_VALID))
|
||||
if (c->pi.flags & IA64_FLAG_SIGTRAMP)
|
||||
{
|
||||
if (write)
|
||||
ret = ia64_get (c, c->sp + 0x10 + SIGFRAME_ARG2_OFF, &loc);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
ret = ia64_get (c, loc + SIGCONTEXT_FLAGS_OFF, &flags);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (!(flags & IA64_SC_FLAG_FPH_VALID))
|
||||
{
|
||||
/* initialize fph partition: */
|
||||
tmp_loc = loc + struct_offset (struct sigcontext, sc_fr[32]);
|
||||
for (i = 32; i < 128; ++i, tmp_loc += 16)
|
||||
if (write)
|
||||
{
|
||||
ret = ia64_putfp (c, tmp_loc, unw.f0);
|
||||
/* initialize fph partition: */
|
||||
tmp_loc = loc + SIGCONTEXT_FR_OFF + 32*16;
|
||||
for (i = 32; i < 128; ++i, tmp_loc += 16)
|
||||
{
|
||||
ret = ia64_putfp (c, tmp_loc, unw.f0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
/* mark fph partition as valid: */
|
||||
ret = ia64_put (c, loc + SIGCONTEXT_FLAGS_OFF,
|
||||
flags | IA64_SC_FLAG_FPH_VALID);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
/* mark fph partition as being valid: */
|
||||
ret = ia64_put (c, loc + struct_offset (struct sigcontext,
|
||||
sc_flags),
|
||||
flags | IA64_SC_FLAG_FPH_VALID);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
else
|
||||
{
|
||||
*valp = unw.f0;
|
||||
return 0;
|
||||
else
|
||||
{
|
||||
*valp = unw.f0;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
loc += struct_offset (struct sigcontext, sc_fr[reg - UNW_IA64_FR]);
|
||||
reg = rotate_fr (c, reg - UNW_IA64_FR) + UNW_IA64_FR;
|
||||
loc = ia64_scratch_loc (c, reg);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue