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Move flushsrs into a better position (after most of the prefetching

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stores are done) to maximize overlap of memory misses.

(Logical change 1.191)
This commit is contained in:
mostang.com!davidm 2004-03-28 00:24:33 +00:00
parent fc7b49b983
commit 5c811e86b0
1 changed files with 16 additions and 15 deletions
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31
src/ia64/getcontext-ia64.S
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@ -41,33 +41,34 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
_Uia64_getcontext: _Uia64_getcontext:
.prologue .prologue
alloc rPFS = ar.pfs, 1, 0, 0, 0 alloc rPFS = ar.pfs, 1, 0, 0, 0
flushrs // save dirty partition on rbs mov.m rFPSR = ar.fpsr
add r2 = SC_MASK, r32 add r2 = SC_MASK, r32
;; ;;
st8 [r2] = r0 // clear sc->sc_mask st8 [r2] = r0 // clear sc->sc_mask
mov.m rFPSR = ar.fpsr mov.m rRSC = ar.rsc
add r2 = GR(1), r32 add r2 = GR(1), r32
;; ;;
mov.m rRSC = ar.rsc
mov.m rBSP = ar.bsp mov.m rBSP = ar.bsp
mov rPR = pr
.save ar.unat, rUNAT .save ar.unat, rUNAT
mov.m rUNAT = ar.unat mov.m rUNAT = ar.unat
.body .body
st8.spill [r2] = r1, (GR(12) - GR(1)) add r3 = GR(12), r32
add r3 = SC_NAT, r32
;; ;;
st8.spill [r2] = sp, (SC_PR - GR(12)) .mem.offset 0,0; st8.spill [r2] = r1, (SC_NAT - GR(1))
lfetch.fault.nt1 [r3] // prefetch nat...ar.lc .mem.offset 8,0; st8.spill [r3] = sp, (SC_PR - GR(12))
adds r3 = FR(2), r32 mov rPR = pr
;; ;;
st8 [r2] = rPR lfetch.fault.nt1 [r2] // prefetch nat...ar.lc
stf.spill [r3] = f2, (FR(16) - FR(2)) st8 [r3] = rPR
add r2 = FR(24), r32 adds r2 = FR(2), r32
;; ;;
stf.spill [r2] = f24, (FR(31) - FR(24)) stf.spill [r2] = f2, (FR(16) - FR(2))
stf.spill [r3] = f16 ;;
stf.spill [r2] = f16, (FR(31) - FR(16))
add r3 = FR(24), r32
;;
flushrs // save dirty partition on rbs
stf.spill [r3] = f24
add r3 = GR(4), r32 add r3 = GR(4), r32
;; ;;
stf.spill [r2] = f31 stf.spill [r2] = f31