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https://github.com/tobast/libunwind-eh_elf.git
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Remove perf-tuning code, make it fit in 80 columns.
(Logical change 1.195)
This commit is contained in:
mostang.com!davidm
parent
3be31f5dcb
commit
50160e1df1
1 changed files with 4 additions and 200 deletions
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@ -39,89 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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.global _Uia64_getcontext
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.global _Uia64_getcontext
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.proc _Uia64_getcontext
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.proc _Uia64_getcontext
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_Uia64_getcontext:
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_Uia64_getcontext:
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#if 0
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add r16 = 0x000, r32
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add r17 = 0x080, r32
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add r18 = 0x100, r32
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add r19 = 0x180, r32
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add r20 = 0x200, r32
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add r21 = 0x280, r32
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add r22 = 0x300, r32
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add r23 = 0x380, r32
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;;
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ld8 r16 = [r16]
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ld8 r17 = [r17]
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ld8 r18 = [r18]
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ld8 r19 = [r19]
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ld8 r20 = [r20]
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ld8 r21 = [r21]
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ld8 r22 = [r22]
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ld8 r23 = [r23]
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;;
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add r16 = r16, r17
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add r18 = r18, r19
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add r20 = r20, r21
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add r22 = r22, r23
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;;
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add r16 = r16, r18
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add r20 = r20, r22
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;;
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add r8 = r16, r20
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br.ret.sptk.many rp
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#elif 0
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add r2 = GR(1), r32;; st8 [r2] = r0
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add r2 = SC_FLAGS, r32;;st8 [r2] = r0
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add r2 = SC_PR, r32;; st8 [r2] = r0
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add r2 = GR(12), r32;; st8 [r2] = r0
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add r2 = FR(2), r32;; stf.spill [r2] = f0
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add r2 = FR(16), r32;; stf.spill [r2] = f0
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add r2 = FR(24), r32;; stf.spill [r2] = f0
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add r2 = FR(31), r32;; stf.spill [r2] = f0
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add r2 = GR(4), r32;; st8 [r2] = r0
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add r2 = GR(5), r32;; st8 [r2] = r0
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add r2 = GR(7), r32;; st8 [r2] = r0
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add r2 = GR(6), r32;; st8 [r2] = r0
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add r2 = BR(0), r32;; st8 [r2] = r0 // 2 cycles
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add r2 = BR(1), r32;; st8 [r2] = r0 // 2 cycles
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add r2 = BR(2), r32;; st8 [r2] = r0 // 2 cycles
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add r2 = BR(4), r32;; st8 [r2] = r0 // 2 cycles
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add r2 = BR(3), r32;; st8 [r2] = r0 // 2 cycles
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add r2 = BR(5), r32;; st8 [r2] = r0 // 2 cycles
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add r2 = SC_PFS, r32;; st8 [r2] = r0 // 2 cycles
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add r2 = SC_LC, r32;; st8 [r2] = r0 // 2 cycles
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add r2 = SC_UNAT, r32;; st8 [r2] = r0 // 5 cycles
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add r2 = SC_BSP, r32;; st8 [r2] = r0 // 12 cycles
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add r2 = SC_FPSR, r32;; st8 [r2] = r0 // 12 cycles
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add r2 = FR(3), r32;; stf.spill [r2] = f0
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add r2 = FR(4), r32;; stf.spill [r2] = f0
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add r2 = FR(5), r32;; stf.spill [r2] = f0
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add r2 = SC_RNAT, r32;; st8 [r2] = r0 // 5 cycles
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add r2 = FR(17), r32;; stf.spill [r2] = f0
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add r2 = FR(18), r32;; stf.spill [r2] = f0
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add r2 = FR(19), r32;; stf.spill [r2] = f0
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add r2 = FR(20), r32;; stf.spill [r2] = f0
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add r2 = FR(21), r32;; stf.spill [r2] = f0
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add r2 = SC_NAT, r32;; st8 [r2] = r0 // last GR spill + 9 cycles
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add r2 = FR(22), r32;; stf.spill [r2] = f0
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add r2 = FR(23), r32;; stf.spill [r2] = f0
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add r2 = FR(25), r32;; stf.spill [r2] = f0
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add r2 = FR(26), r32;; stf.spill [r2] = f0
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add r2 = FR(27), r32;; stf.spill [r2] = f0
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add r2 = FR(28), r32;; stf.spill [r2] = f0
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add r2 = FR(29), r32;; stf.spill [r2] = f0
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add r2 = FR(30), r32;; stf.spill [r2] = f0
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br.ret.sptk.many rp
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#elif 1
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.prologue
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.prologue
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alloc rPFS = ar.pfs, 1, 0, 0, 0 // M2
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alloc rPFS = ar.pfs, 1, 0, 0, 0 // M2
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mov rPR = pr // I0, 2 cycles
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mov rPR = pr // I0, 2 cycles
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@ -135,17 +52,17 @@ _Uia64_getcontext:
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dep.z rFLAGS = -1, IA64_SC_FLAG_SYNCHRONOUS_BIT, 1 // I0, 1 cycle
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dep.z rFLAGS = -1, IA64_SC_FLAG_SYNCHRONOUS_BIT, 1 // I0, 1 cycle
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;;
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;;
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mov.m rRSC = ar.rsc // M2, 12 cycles
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mov.m rRSC = ar.rsc // M2, 12 cyc.
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st8 [r2] = rFLAGS, (SC_PR - SC_FLAGS) // M3
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st8 [r2] = rFLAGS, (SC_PR - SC_FLAGS) // M3
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add r3 = FR(2), in0
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add r3 = FR(2), in0
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;;
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;;
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mov.m rBSP = ar.bsp // M2, 12 cycles
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mov.m rBSP = ar.bsp // M2, 12 cyc.
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st8 [r2] = rPR, (GR(12) - SC_PR) // M3
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st8 [r2] = rPR, (GR(12) - SC_PR) // M3
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add r8 = FR(16), in0
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add r8 = FR(16), in0
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;;
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;;
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mov.m rFPSR = ar.fpsr // M2, 12 cycles
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mov.m rFPSR = ar.fpsr // M2, 12 cyc.
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st8.spill [r2] = r12, (GR(4) - GR(12)) // M3
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st8.spill [r2] = r12, (GR(4) - GR(12)) // M3
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add r9 = FR(24), in0
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add r9 = FR(24), in0
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;;
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;;
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@ -190,7 +107,7 @@ _Uia64_getcontext:
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mov.i rLC = ar.lc // I0, 2 cycles
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mov.i rLC = ar.lc // I0, 2 cycles
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;;
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;;
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mov.m ar.rsc = rTMP // put RSE into lazy mode // M2, ?? cycles
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mov.m ar.rsc = rTMP // put RSE into lazy mode // M2, ? cycles
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st8 [r2] = rB3, (BR(5) - BR(3)) // M3, bank 0
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st8 [r2] = rB3, (BR(5) - BR(3)) // M3, bank 0
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extr.u rPOS = rPOS, 3, 6 // get NaT bitnr for r0 // I0
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extr.u rPOS = rPOS, 3, 6 // get NaT bitnr for r0 // I0
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;;
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;;
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@ -253,117 +170,4 @@ _Uia64_getcontext:
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stf.spill [r9] = f30 // M2
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stf.spill [r9] = f30 // M2
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mov r8 = 0
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mov r8 = 0
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br.ret.sptk.many rp
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br.ret.sptk.many rp
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#elif 0
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.prologue
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alloc rPFS = ar.pfs, 1, 0, 0, 0
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add r3 = SC_MASK, r32
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;;
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st8 [r3] = r0 // clear sc->sc_mask
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flushrs // save dirty partition on rbs
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mov.m rFPSR = ar.fpsr
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mov.m rRSC = ar.rsc
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add r2 = SC_GR+1*8, r32
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;;
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mov.m rBSP = ar.bsp
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.save ar.unat, rUNAT
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mov.m rUNAT = ar.unat
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.body
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add r3 = SC_GR+4*8, r32
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;;
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.mem.offset 0,0; st8.spill [r2] = r1, (5*8 - 1*8)
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.mem.offset 8,0; st8.spill [r3] = r4, 16
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;;
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.mem.offset 0,0; st8.spill [r2] = r5, 16
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.mem.offset 8,0; st8.spill [r3] = r6, 48
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and rTMP = ~0x3, rRSC
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;;
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.mem.offset 0,0; st8.spill [r2] = r7, (SC_FR+2*16-(SC_GR+7*8))
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.mem.offset 8,0; st8.spill [r3] = sp, (SC_FR+3*16-(SC_GR+12*8))
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;;
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mov.m ar.rsc = rTMP // put RSE into enforced lazy mode
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mov.m rNAT = ar.unat
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mov.i rLC = ar.lc
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;;
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mov.m rRNAT = ar.rnat
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mov.m ar.rsc = rRSC // restore RSE mode
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mov rPR = pr
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/*
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* Rotate NaT bits by rPOS positions to the right:
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*/
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stf.spill [r2] = f2, 32
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stf.spill [r3] = f3, 32
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add rPOS = SC_GR, r32 // rPOS <- &sc_gr[0]
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;;
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stf.spill [r2] = f4, (16*16-4*16)
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stf.spill [r3] = f5, (17*16-5*16)
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extr.u rPOS = rPOS, 3, 6 // get NaT bit number for r0
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;;
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stf.spill [r2] = f16, 32
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stf.spill [r3] = f17, 32
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sub rCPOS = 64, rPOS
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;;
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stf.spill [r2] = f18, 32
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stf.spill [r3] = f19, 32
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shr.u rTMP = rNAT, rPOS
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;;
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stf.spill [r2] = f20, 32
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stf.spill [r3] = f21, 32
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shl rNAT = rNAT, rCPOS
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;;
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stf.spill [r2] = f22, 32
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stf.spill [r3] = f23, 32
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or rNAT = rNAT, rTMP
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;;
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stf.spill [r2] = f24, 32
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stf.spill [r3] = f25, 32
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mov r8 = 0
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;;
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stf.spill [r2] = f26, 32
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stf.spill [r3] = f27, 32
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mov r9 = 1
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;;
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stf.spill [r2] = f28, 32
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stf.spill [r3] = f29, 32
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mov rB0 = b0
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;;
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stf.spill [r2] = f30, 32
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stf.spill [r3] = f31, 32
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mov rB1 = b1
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;;
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mov ar.unat = rUNAT // done with integer regs; restore caller's UNaT
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add r2 = SC_NAT, r32
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add r3 = SC_BSP, r32
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;;
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st8 [r2] = rNAT, (SC_RNAT-SC_NAT)
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st8 [r3] = rBSP, (SC_UNAT-SC_BSP)
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mov rB2 = b2
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;;
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st8 [r2] = rRNAT, (SC_FPSR-SC_RNAT)
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st8 [r3] = rUNAT, (SC_PFS-SC_UNAT)
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mov rB3 = b3
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;;
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st8 [r2] = rFPSR, (SC_LC-SC_FPSR)
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st8 [r3] = rPFS, (SC_PR-SC_PFS)
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mov rB4 = b4
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;;
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st8 [r2] = rLC, (SC_BR+0*8-SC_LC)
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st8 [r3] = rPR, (SC_BR+1*8-SC_PR)
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mov rB5 = b5
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;;
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st8 [r2] = rB0, 16
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st8 [r3] = rB1, 16
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;;
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st8 [r2] = rB2, 16
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st8 [r3] = rB3, 16
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;;
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st8 [r2] = rB4
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st8 [r3] = rB5
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br.ret.sptk.many rp
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#endif
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.endp _Uia64_getcontext
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.endp _Uia64_getcontext
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