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Adjust for IA64_FLAG_BIG_ENDIAN -> as->big_endian change.
(ia64_access_regs): Call ia64_make_proc_info() to ensure c->pi.gp is valid before returning it. 2002/12/11 12:27:31-08:00 mostang.com!davidm Rename: src/ia64/regs.c -> src/ia64/Gregs.c (Logical change 1.30)
This commit is contained in:
mostang.com!davidm
parent
d3da356368
commit
3919f4ffb6
1 changed files with 494 additions and 0 deletions
494
src/ia64/Gregs.c
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494
src/ia64/Gregs.c
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@ -0,0 +1,494 @@
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/* libunwind - a platform-independent unwind library
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Copyright (C) 2001-2002 Hewlett-Packard Co
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
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This file is part of libunwind.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#include <assert.h>
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#include "offsets.h"
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#include "regs.h"
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#include "rse.h"
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#include "unwind_i.h"
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unw_word_t
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ia64_scratch_loc (struct ia64_cursor *c, unw_regnum_t reg)
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{
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unw_word_t loc = c->sigcontext_loc;
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if (loc)
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{
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switch (reg)
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{
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case UNW_IA64_NAT + 2 ... UNW_IA64_NAT + 3:
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case UNW_IA64_NAT + 8 ... UNW_IA64_NAT + 31:
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loc += SIGCONTEXT_NAT_OFF;
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break;
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case UNW_IA64_GR + 2 ... UNW_IA64_GR + 3:
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case UNW_IA64_GR + 8 ... UNW_IA64_GR + 31:
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loc += SIGCONTEXT_GR_OFF + 8*reg;
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break;
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case UNW_IA64_FR + 6 ... UNW_IA64_FR + 15:
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loc += SIGCONTEXT_FR_OFF + 16*(reg - UNW_IA64_FR);
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break;
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case UNW_IA64_FR + 32 ... UNW_IA64_FR + 127:
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loc += SIGCONTEXT_FR_OFF + 16*(reg - UNW_IA64_FR);
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break;
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case UNW_IA64_BR + 0: loc += SIGCONTEXT_BR_OFF + 0; break;
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case UNW_IA64_BR + 6: loc += SIGCONTEXT_BR_OFF + 6*8; break;
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case UNW_IA64_BR + 7: loc += SIGCONTEXT_BR_OFF + 7*8; break;
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case UNW_IA64_AR_RSC: loc += SIGCONTEXT_AR_RSC_OFF; break;
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case UNW_IA64_AR_25: loc += SIGCONTEXT_AR_25_OFF; break;
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case UNW_IA64_AR_26: loc += SIGCONTEXT_AR_26_OFF; break;
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case UNW_IA64_AR_CCV: loc += SIGCONTEXT_AR_CCV; break;
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}
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return loc;
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}
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else
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return IA64_REG_LOC (c, reg);
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}
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static inline int
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update_nat (struct ia64_cursor *c, unw_word_t nat_loc, unw_word_t mask,
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unw_word_t *valp, int write)
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{
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unw_word_t nat_word;
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int ret;
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ret = ia64_get (c, nat_loc, &nat_word);
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if (ret < 0)
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return ret;
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if (write)
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{
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if (*valp)
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nat_word |= mask;
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else
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nat_word &= ~mask;
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ret = ia64_put (c, nat_loc, nat_word);
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}
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else
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*valp = (nat_word & mask) != 0;
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return ret;
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}
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static int
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access_nat (struct ia64_cursor *c, unw_word_t loc, unw_word_t reg_loc,
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unw_word_t *valp, int write)
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{
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unw_word_t nat_loc = -8, mask = 0, sc_addr;
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unw_fpreg_t tmp;
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int ret, reg;
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if (IA64_IS_FP_LOC (reg_loc))
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{
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/* NaT bit is saved as a NaTVal. This happens when a general
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register is saved to a floating-point register. */
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if (write)
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{
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if (*valp)
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{
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if (c->as->big_endian)
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ret = ia64_putfp (c, reg_loc, unw.nat_val_be);
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else
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ret = ia64_putfp (c, reg_loc, unw.nat_val_le);
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}
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else
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{
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unw_fpreg_t tmp;
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ret = ia64_getfp (c, reg_loc, &tmp);
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if (ret < 0)
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return ret;
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/* Reset the exponent to 0x1003e so that the significand
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will be interpreted as an integer value. */
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if (c->as->big_endian)
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tmp.raw.bits[0] = unw.int_val_be.raw.bits[0];
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else
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tmp.raw.bits[1] = unw.int_val_le.raw.bits[1];
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ret = ia64_putfp (c, reg_loc, tmp);
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}
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}
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else
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{
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ret = ia64_getfp (c, reg_loc, &tmp);
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if (ret < 0)
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return ret;
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if (c->as->big_endian)
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*valp = (memcmp (&tmp, &unw.nat_val_be, sizeof (tmp)) == 0);
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else
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*valp = (memcmp (&tmp, &unw.nat_val_le, sizeof (tmp)) == 0);
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}
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return ret;
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}
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if (IA64_IS_MEMSTK_NAT (loc))
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{
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nat_loc = IA64_GET_LOC (loc) << 3;
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mask = (unw_word_t) 1 << ia64_rse_slot_num (reg_loc);
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}
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else
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{
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reg = IA64_GET_LOC (loc);
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assert (reg >= 0 && reg < 128);
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if (!reg)
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{
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/* NaT bit is not saved. This happens if a general register
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is saved to a branch register. Since the NaT bit gets
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lost, we need to drop it here, too. Note that if the NaT
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bit had been set when the save occurred, it would have
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caused a NaT consumption fault. */
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if (write)
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{
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if (*valp)
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return -UNW_EBADREG; /* can't set NaT bit */
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}
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else
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*valp = 0;
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return 0;
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}
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if (reg >= 4 && reg <= 7)
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{
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/* NaT bit is saved in a NaT register. This happens when a
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general register is saved to another general
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register. */
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#ifdef UNW_LOCAL_ONLY
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ucontext_t *uc = c->as_arg;
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mask = ((unw_word_t) 1) << reg;
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nat_loc = (unw_word_t) &uc->uc_mcontext.sc_nat;
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#else
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if (write)
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ret = ia64_put (c, IA64_REG_LOC (c, UNW_IA64_NAT + reg), *valp);
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else
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ret = ia64_get (c, IA64_REG_LOC (c, UNW_IA64_NAT + reg), valp);
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return ret;
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#endif
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}
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else if (reg >= 32)
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{
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/* NaT bit is saved in a stacked register. */
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nat_loc = ia64_rse_rnat_addr (reg_loc); /* XXX looks wrong */
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if (nat_loc > c->rbs_top)
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nat_loc = c->top_rnat_loc;
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mask = (unw_word_t) 1 << ia64_rse_slot_num (reg_loc);
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}
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else
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{
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/* NaT bit is saved in a scratch register. */
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sc_addr = c->sigcontext_loc;
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if (sc_addr)
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{
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nat_loc = sc_addr + SIGCONTEXT_NAT_OFF;
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mask = (unw_word_t) 1 << reg;
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}
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else
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{
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if (write)
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return ia64_put (c, loc, *valp);
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else
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return ia64_get (c, loc, valp);
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}
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}
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}
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return update_nat (c, nat_loc, mask, valp, write);
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}
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int
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ia64_access_reg (struct ia64_cursor *c, unw_regnum_t reg, unw_word_t *valp,
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int write)
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{
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unw_word_t loc = -8, reg_loc, nat, nat_loc, cfm, mask, pr;
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int ret, readonly = 0;
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switch (reg)
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{
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/* frame registers: */
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case UNW_IA64_BSP:
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if (write)
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return -UNW_EREADONLYREG;
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*valp = c->bsp;
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return 0;
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case UNW_REG_SP:
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if (write)
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return -UNW_EREADONLYREG;
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*valp = c->sp;
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return 0;
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case UNW_REG_IP:
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if (write)
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c->ip = *valp; /* also update the IP cache */
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loc = c->ip_loc;
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break;
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/* preserved registers: */
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case UNW_IA64_GR + 4 ... UNW_IA64_GR + 7:
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loc = (&c->r4_loc)[reg - (UNW_IA64_GR + 4)];
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break;
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case UNW_IA64_NAT + 4 ... UNW_IA64_NAT + 7:
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loc = (&c->nat4_loc)[reg - (UNW_IA64_NAT + 4)];
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reg_loc = (&c->r4_loc)[reg - (UNW_IA64_NAT + 4)];
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return access_nat (c, loc, reg_loc, valp, write);
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case UNW_IA64_AR_BSP: loc = c->bsp_loc; break;
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case UNW_IA64_AR_BSPSTORE: loc = c->bspstore_loc; break;
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case UNW_IA64_AR_PFS: loc = c->pfs_loc; break;
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case UNW_IA64_AR_RNAT: loc = c->rnat_loc; break;
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case UNW_IA64_AR_UNAT: loc = c->unat_loc; break;
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case UNW_IA64_AR_LC: loc = c->lc_loc; break;
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case UNW_IA64_AR_FPSR: loc = c->fpsr_loc; break;
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case UNW_IA64_BR + 1: loc = c->b1_loc; break;
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case UNW_IA64_BR + 2: loc = c->b2_loc; break;
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case UNW_IA64_BR + 3: loc = c->b3_loc; break;
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case UNW_IA64_BR + 4: loc = c->b4_loc; break;
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case UNW_IA64_BR + 5: loc = c->b5_loc; break;
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case UNW_IA64_CFM: loc = c->cfm_loc; break;
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case UNW_IA64_PR:
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if (write)
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{
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c->pr = *valp; /* update the predicate cache */
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pr = pr_ltop (c, *valp);
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return ia64_put (c, c->pr_loc, pr);
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}
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else
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{
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ret = ia64_get (c, c->pr_loc, &pr);
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if (ret < 0)
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return ret;
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*valp = pr_ptol (c, pr);
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}
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return 0;
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case UNW_IA64_GR + 32 ... UNW_IA64_GR + 127: /* stacked reg */
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reg = rotate_gr (c, reg - UNW_IA64_GR) + UNW_IA64_GR;
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if (reg < 0)
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return -UNW_EBADREG;
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loc = ia64_rse_skip_regs (c->bsp, reg - (UNW_IA64_GR + 32));
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break;
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case UNW_IA64_NAT + 32 ... UNW_IA64_NAT + 127: /* stacked reg */
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reg = rotate_gr (c, reg - UNW_IA64_NAT) + UNW_IA64_NAT;
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if (reg < 0)
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return -UNW_EBADREG;
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loc = ia64_rse_skip_regs (c->bsp, reg - (UNW_IA64_NAT + 32));
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nat_loc = ia64_rse_rnat_addr (loc);
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if (nat_loc > c->rbs_top)
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nat_loc = c->top_rnat_loc;
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mask = (unw_word_t) 1 << ia64_rse_slot_num (loc);
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return update_nat (c, nat_loc, mask, valp, write);
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case UNW_IA64_AR_EC:
|
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ret = ia64_get (c, c->cfm_loc, &cfm);
|
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if (ret < 0)
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return ret;
|
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if (write)
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ret = ia64_put (c, c->cfm_loc, ((cfm & ~((unw_word_t) 0x3f << 52))
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| (*valp & 0x3f) << 52));
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else
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*valp = (cfm >> 52) & 0x3f;
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return ret;
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|
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/* scratch & special registers: */
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case UNW_IA64_GR + 0:
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if (write)
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return -UNW_EREADONLYREG;
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*valp = 0;
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return 0;
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case UNW_IA64_GR + 1: /* global pointer */
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if (write)
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return -UNW_EREADONLYREG;
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/* ensure c->pi is up-to-date: */
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if ((ret = ia64_make_proc_info (c)) < 0)
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return ret;
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*valp = c->pi.gp;
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return 0;
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case UNW_IA64_NAT + 0:
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case UNW_IA64_NAT + 1: /* global pointer */
|
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if (write)
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return -UNW_EREADONLYREG;
|
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*valp = 0;
|
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return 0;
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case UNW_IA64_NAT + 2 ... UNW_IA64_NAT + 3:
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case UNW_IA64_NAT + 8 ... UNW_IA64_NAT + 31:
|
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loc = ia64_scratch_loc (c, reg);
|
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if (c->sigcontext_loc)
|
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{
|
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mask = (unw_word_t) 1 << (reg - UNW_IA64_NAT);
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|
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ret = ia64_get (c, loc, &nat);
|
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if (ret < 0)
|
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return ret;
|
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|
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if (write)
|
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{
|
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if (*valp)
|
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nat |= mask;
|
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else
|
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nat &= ~mask;
|
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ret = ia64_put (c, loc, nat);
|
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}
|
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else
|
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*valp = (nat & mask) != 0;
|
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return ret;
|
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}
|
||||
break;
|
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|
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case UNW_IA64_GR + 15 ... UNW_IA64_GR + 18:
|
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if (c->is_signal_frame)
|
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loc = ia64_scratch_loc (c, reg);
|
||||
else
|
||||
{
|
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if (write)
|
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c->eh_args[reg - (UNW_IA64_GR + 15)] = *valp;
|
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else
|
||||
*valp = c->eh_args[reg - (UNW_IA64_GR + 15)] = *valp;
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case UNW_IA64_GR + 2 ... UNW_IA64_GR + 3:
|
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case UNW_IA64_GR + 8 ... UNW_IA64_GR + 14:
|
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case UNW_IA64_GR + 19 ... UNW_IA64_GR + 31:
|
||||
case UNW_IA64_BR + 0:
|
||||
case UNW_IA64_BR + 6:
|
||||
case UNW_IA64_BR + 7:
|
||||
case UNW_IA64_AR_RSC:
|
||||
case UNW_IA64_AR_25:
|
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case UNW_IA64_AR_26:
|
||||
case UNW_IA64_AR_CCV:
|
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loc = ia64_scratch_loc (c, reg);
|
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break;
|
||||
|
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default:
|
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dprintf ("%s: bad register number %d\n", __FUNCTION__, reg);
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return -UNW_EBADREG;
|
||||
}
|
||||
|
||||
if (write)
|
||||
{
|
||||
if (readonly)
|
||||
return -UNW_EREADONLYREG;
|
||||
return ia64_put (c, loc, *valp);
|
||||
}
|
||||
else
|
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return ia64_get (c, loc, valp);
|
||||
}
|
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|
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int
|
||||
ia64_access_fpreg (struct ia64_cursor *c, int reg, unw_fpreg_t *valp,
|
||||
int write)
|
||||
{
|
||||
unw_word_t loc = -8, flags, tmp_loc;
|
||||
int ret, i;
|
||||
|
||||
switch (reg)
|
||||
{
|
||||
case UNW_IA64_FR + 0:
|
||||
if (write)
|
||||
return -UNW_EREADONLYREG;
|
||||
*valp = unw.f0;
|
||||
return 0;
|
||||
|
||||
case UNW_IA64_FR + 1:
|
||||
if (write)
|
||||
return -UNW_EREADONLYREG;
|
||||
|
||||
if (c->as->big_endian)
|
||||
*valp = unw.f1_be;
|
||||
else
|
||||
*valp = unw.f1_le;
|
||||
return 0;
|
||||
|
||||
case UNW_IA64_FR + 2: loc = c->f2_loc; break;
|
||||
case UNW_IA64_FR + 3: loc = c->f3_loc; break;
|
||||
case UNW_IA64_FR + 4: loc = c->f4_loc; break;
|
||||
case UNW_IA64_FR + 5: loc = c->f5_loc; break;
|
||||
case UNW_IA64_FR + 16 ... UNW_IA64_FR + 31:
|
||||
loc = c->fr_loc[reg - (UNW_IA64_FR + 16)];
|
||||
break;
|
||||
|
||||
case UNW_IA64_FR + 6 ... UNW_IA64_FR + 15:
|
||||
loc = ia64_scratch_loc (c, reg);
|
||||
break;
|
||||
|
||||
case UNW_IA64_FR + 32 ... UNW_IA64_FR + 127:
|
||||
loc = c->sigcontext_loc;
|
||||
if (loc)
|
||||
{
|
||||
ret = ia64_get (c, loc + SIGCONTEXT_FLAGS_OFF, &flags);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (!(flags & IA64_SC_FLAG_FPH_VALID))
|
||||
{
|
||||
if (write)
|
||||
{
|
||||
/* initialize fph partition: */
|
||||
tmp_loc = loc + SIGCONTEXT_FR_OFF + 32*16;
|
||||
for (i = 32; i < 128; ++i, tmp_loc += 16)
|
||||
{
|
||||
ret = ia64_putfp (c, tmp_loc, unw.f0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
/* mark fph partition as valid: */
|
||||
ret = ia64_put (c, loc + SIGCONTEXT_FLAGS_OFF,
|
||||
flags | IA64_SC_FLAG_FPH_VALID);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
else
|
||||
{
|
||||
*valp = unw.f0;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
reg = rotate_fr (c, reg - UNW_IA64_FR) + UNW_IA64_FR;
|
||||
loc = ia64_scratch_loc (c, reg);
|
||||
break;
|
||||
}
|
||||
|
||||
if (write)
|
||||
return ia64_putfp (c, loc, *valp);
|
||||
else
|
||||
return ia64_getfp (c, loc, valp);
|
||||
}
|
||||
Loading…
Reference in a new issue