2002-02-16 00:22:05 +01:00
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/* libunwind - a platform-independent unwind library
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Copyright (C) 2001-2002 Hewlett-Packard Co
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
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This file is part of libunwind.
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libunwind is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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libunwind is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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As a special exception, if you link this library with other files to
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produce an executable, this library does not by itself cause the
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resulting executable to be covered by the GNU General Public License.
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This exception does not however invalidate any other reasons why the
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executable file might be covered by the GNU General Public
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License. */
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#include <assert.h>
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2002-02-22 22:58:53 +01:00
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#include "offsets.h"
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#include "rse.h"
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#include "unwind_i.h"
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2002-02-16 00:22:05 +01:00
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unw_word_t
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2002-02-22 22:58:53 +01:00
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ia64_scratch_loc (struct ia64_cursor *c, unw_regnum_t reg)
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2002-02-16 00:22:05 +01:00
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{
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2002-02-22 22:58:53 +01:00
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unw_word_t loc;
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if (c->pi.flags & IA64_FLAG_SIGTRAMP)
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{
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if (ia64_get (c, c->sp + 0x10 + SIGFRAME_ARG2_OFF, &loc) < 0)
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return 0;
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switch (reg)
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{
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case UNW_IA64_NAT + 2 ... UNW_IA64_NAT + 3:
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case UNW_IA64_NAT + 8 ... UNW_IA64_NAT + 31:
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loc += SIGCONTEXT_NAT_OFF;
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break;
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case UNW_IA64_GR + 2 ... UNW_IA64_GR + 3:
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case UNW_IA64_GR + 8 ... UNW_IA64_GR + 31:
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loc += SIGCONTEXT_GR_OFF + 8*reg;
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break;
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case UNW_IA64_FR + 6 ... UNW_IA64_FR + 15:
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loc += SIGCONTEXT_FR_OFF + 16*(reg - UNW_IA64_FR);
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break;
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2002-02-16 00:22:05 +01:00
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2002-02-22 22:58:53 +01:00
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case UNW_IA64_FR + 32 ... UNW_IA64_FR + 127:
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loc += SIGCONTEXT_FR_OFF + 16*(reg - UNW_IA64_FR);
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break;
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2002-02-16 00:22:05 +01:00
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2002-02-22 22:58:53 +01:00
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case UNW_IA64_BR + 0: loc += SIGCONTEXT_BR_OFF + 0; break;
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case UNW_IA64_BR + 7: loc += SIGCONTEXT_BR_OFF + 7*8; break;
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case UNW_IA64_AR_RSC: loc += SIGCONTEXT_AR_RSC_OFF; break;
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case UNW_IA64_AR_25: loc += SIGCONTEXT_AR_25_OFF; break;
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case UNW_IA64_AR_26: loc += SIGCONTEXT_AR_26_OFF; break;
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case UNW_IA64_AR_CCV: loc += SIGCONTEXT_AR_CCV; break;
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}
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2002-02-16 00:22:05 +01:00
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2002-02-22 22:58:53 +01:00
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return loc;
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}
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else
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return IA64_REG_LOC (reg);
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2002-02-16 00:22:05 +01:00
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}
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/* Apply rotation to a general register. The number REG must be in
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the range of 0-127. */
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static inline int
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rotate_gr (struct ia64_cursor *c, int reg)
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{
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unsigned int rrb_gr, sor;
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unw_word_t cfm;
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int preg, ret;
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ret = ia64_get (c, c->cfm_loc, &cfm);
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if (ret < 0)
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return ret;
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sor = 8 * ((cfm >> 14) & 0xf);
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rrb_gr = (cfm >> 18) & 0x7f;
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if ((unsigned) (reg - 32) > sor)
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preg = reg; /* register not part of the rotating partition */
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else
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{
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preg = reg + rrb_gr; /* apply rotation */
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if (preg > 32 + sor)
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preg -= sor; /* wrap around */
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}
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debug (100, "%s: sor=%u rrb.gr=%u, r%d -> r%d\n", __FUNCTION__, sor, rrb_gr,
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reg, preg);
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return preg;
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}
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/* Apply rotation to a floating-point register. The number REG must
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be in the range of 0-127. */
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static inline int
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rotate_fr (struct ia64_cursor *c, int reg)
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{
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unsigned int rrb_fr;
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unw_word_t cfm;
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int preg, ret;
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ret = ia64_get (c, c->cfm_loc, &cfm);
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if (ret < 0)
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return ret;
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rrb_fr = (cfm >> 25) & 0x7f;
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if (reg < 32)
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preg = reg; /* register not part of the rotating partition */
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else
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{
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preg = reg + rrb_fr; /* apply rotation */
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if (preg > 127)
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preg -= 96; /* wrap around */
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}
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debug (100, "%s: rrb.fr=%u, f%d -> f%d\n", __FUNCTION__, rrb_fr, reg, preg);
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return preg;
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}
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/* Apply logical-to-physical rotation. */
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static inline unw_word_t
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pr_ltop (struct ia64_cursor *c, unw_word_t pr)
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{
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unw_word_t rrb_pr, mask, rot, cfm;
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int ret;
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ret = ia64_get (c, c->cfm_loc, &cfm);
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if (ret < 0)
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return ret;
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rrb_pr = (cfm >> 32) & 0x3f;
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rot = pr >> 16;
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mask = ((unw_word_t) 1 << rrb_pr) - 1;
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rot = ((pr & mask) << (48 - rrb_pr)) | ((pr >> rrb_pr) & mask);
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return (pr & 0xffff) | (rot << 16);
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}
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/* Apply physical-to-logical rotation. */
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static inline unw_word_t
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pr_ptol (struct ia64_cursor *c, unw_word_t pr)
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{
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unw_word_t rrb_pr, mask, rot, cfm;
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int ret;
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ret = ia64_get (c, c->cfm_loc, &cfm);
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if (ret < 0)
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return ret;
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rrb_pr = 48 - ((cfm >> 32) & 0x3f);
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rot = pr >> 16;
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mask = ((unw_word_t) 1 << rrb_pr) - 1;
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rot = ((pr & mask) << (48 - rrb_pr)) | ((pr >> rrb_pr) & mask);
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return (pr & 0xffff) | (rot << 16);
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}
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static inline int
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update_nat (struct ia64_cursor *c, unw_word_t nat_loc, unw_word_t mask,
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unw_word_t *valp, int write)
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{
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unw_word_t nat_word;
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int ret;
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ret = ia64_get (c, nat_loc, &nat_word);
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if (ret < 0)
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return ret;
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if (write)
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{
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if (*valp)
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nat_word |= mask;
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else
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nat_word &= ~mask;
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ret = ia64_put (c, nat_loc, nat_word);
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}
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else
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*valp = (nat_word & mask) != 0;
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return ret;
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}
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static int
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access_nat (struct ia64_cursor *c, unw_word_t loc, unw_word_t reg_loc,
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unw_word_t *valp, int write)
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{
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unw_word_t nat_loc = -8, mask = 0, sc_addr;
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unw_fpreg_t tmp;
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2002-02-22 22:58:53 +01:00
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int ret, reg;
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2002-02-16 00:22:05 +01:00
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if (IA64_IS_FP_LOC (reg_loc))
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{
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/* NaT bit is saved as a NaTVal. This happens when a general
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register is saved to a floating-point register. */
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if (write)
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{
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if (*valp)
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{
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if (c->pi.flags & IA64_FLAG_BIG_ENDIAN)
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ret = ia64_putfp (c, reg_loc, unw.nat_val_be);
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else
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ret = ia64_putfp (c, reg_loc, unw.nat_val_le);
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}
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else
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{
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unw_fpreg_t tmp;
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ret = ia64_getfp (c, reg_loc, &tmp);
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if (ret < 0)
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return ret;
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/* Reset the exponent to 0x1003e so that the significand
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will be interpreted as an integer value. */
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if (c->pi.flags & IA64_FLAG_BIG_ENDIAN)
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tmp.raw.bits[0] = unw.int_val_be.raw.bits[0];
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else
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tmp.raw.bits[1] = unw.int_val_le.raw.bits[1];
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ret = ia64_putfp (c, reg_loc, tmp);
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}
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}
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else
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{
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ret = ia64_getfp (c, reg_loc, &tmp);
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if (ret < 0)
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return ret;
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if (c->pi.flags & IA64_FLAG_BIG_ENDIAN)
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*valp = (memcmp (&tmp, &unw.nat_val_be, sizeof (tmp)) == 0);
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else
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*valp = (memcmp (&tmp, &unw.nat_val_le, sizeof (tmp)) == 0);
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}
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return ret;
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}
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if (IA64_IS_MEMSTK_NAT (loc))
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{
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nat_loc = IA64_GET_LOC (loc) << 3;
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2002-02-22 22:58:53 +01:00
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mask = (unw_word_t) 1 << ia64_rse_slot_num (reg_loc);
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2002-02-16 00:22:05 +01:00
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}
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else
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{
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2002-02-22 22:58:53 +01:00
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reg = IA64_GET_LOC (loc);
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assert (reg >= 0 && reg < 128);
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if (!reg)
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2002-02-16 00:22:05 +01:00
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{
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/* NaT bit is not saved. This happens if a general register
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is saved to a branch register. Since the NaT bit gets
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lost, we need to drop it here, too. Note that if the NaT
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bit had been set when the save occurred, it would have
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caused a NaT consumption fault. */
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if (write)
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{
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if (*valp)
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return -UNW_EBADREG; /* can't set NaT bit */
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}
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else
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*valp = 0;
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return 0;
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}
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2002-02-22 22:58:53 +01:00
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if (reg >= 4 && reg <= 7)
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2002-02-16 00:22:05 +01:00
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{
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/* NaT bit is saved in a NaT register. This happens when a
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general register is saved to another general
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register. */
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if (write)
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2002-02-22 22:58:53 +01:00
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ret = ia64_put (c, UNW_IA64_NAT + reg, *valp);
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2002-02-16 00:22:05 +01:00
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else
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2002-02-22 22:58:53 +01:00
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ret = ia64_get (c, UNW_IA64_NAT + reg, valp);
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2002-02-16 00:22:05 +01:00
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return ret;
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}
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2002-02-22 22:58:53 +01:00
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else if (reg >= 32)
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2002-02-16 00:22:05 +01:00
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{
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/* NaT bit is saved in a stacked register. */
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2002-02-22 22:58:53 +01:00
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nat_loc = (intptr_t) ia64_rse_rnat_addr (reg_loc);
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2002-02-16 00:22:05 +01:00
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if (nat_loc > c->rbs_top)
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nat_loc = c->top_rnat_loc;
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2002-02-22 22:58:53 +01:00
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mask = (intptr_t) 1 << ia64_rse_slot_num (reg_loc);
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2002-02-16 00:22:05 +01:00
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}
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else
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{
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/* NaT bit is saved in a scratch register. */
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2002-02-22 22:58:53 +01:00
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if (c->pi.flags & IA64_FLAG_SIGTRAMP)
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{
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ret = ia64_get (c, c->sp + 0x10 + SIGFRAME_ARG2_OFF, &sc_addr);
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if (ret < 0)
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return ret;
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2002-02-16 00:22:05 +01:00
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2002-02-22 22:58:53 +01:00
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nat_loc = sc_addr + SIGCONTEXT_NAT_OFF;
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mask = (unw_word_t) 1 << reg;
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}
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else
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{
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if (write)
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return ia64_put (c, loc, *valp);
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else
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return ia64_get (c, loc, valp);
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}
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2002-02-16 00:22:05 +01:00
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}
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}
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return update_nat (c, nat_loc, mask, valp, write);
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}
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int
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ia64_access_reg (struct ia64_cursor *c, unw_regnum_t reg, unw_word_t *valp,
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int write)
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{
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2002-02-22 22:58:53 +01:00
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unw_word_t loc = -8, reg_loc, nat, nat_loc, cfm, mask, pr;
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2002-02-16 00:22:05 +01:00
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int ret, readonly = 0;
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switch (reg)
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{
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/* frame registers: */
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case UNW_IA64_CURRENT_BSP:
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if (write)
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return -UNW_EREADONLYREG;
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*valp = c->bsp;
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return 0;
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case UNW_REG_SP:
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case UNW_REG_PROC_START:
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case UNW_REG_HANDLER:
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case UNW_REG_LSDA:
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if (write)
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return -UNW_EREADONLYREG;
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switch (reg)
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{
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case UNW_REG_SP: *valp = c->sp; break;
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case UNW_REG_PROC_START:*valp = c->pi.proc_start; break;
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case UNW_REG_LSDA:
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2002-02-22 22:58:53 +01:00
|
|
|
*valp = (intptr_t) (c->pi.pers_addr + 1);
|
2002-02-16 00:22:05 +01:00
|
|
|
break;
|
|
|
|
case UNW_REG_HANDLER:
|
|
|
|
if (c->pi.flags & IA64_FLAG_HAS_HANDLER)
|
|
|
|
/* *c->pers_addr is the linkage-table offset of the word
|
|
|
|
that stores the address of the personality routine's
|
|
|
|
function descriptor. */
|
2002-02-22 22:58:53 +01:00
|
|
|
return ia64_get (c, *c->pi.pers_addr + c->pi.gp, valp);
|
2002-02-16 00:22:05 +01:00
|
|
|
else
|
|
|
|
*valp = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case UNW_REG_IP:
|
2002-02-22 22:58:53 +01:00
|
|
|
if (write)
|
|
|
|
c->ip = *valp; /* also update the IP cache */
|
|
|
|
loc = c->ip_loc;
|
2002-02-16 00:22:05 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* preserved registers: */
|
|
|
|
|
2002-02-22 22:58:53 +01:00
|
|
|
case UNW_IA64_GR + 4 ... UNW_IA64_GR + 7:
|
|
|
|
loc = (&c->r4_loc)[reg - (UNW_IA64_GR + 4)];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case UNW_IA64_NAT + 4 ... UNW_IA64_NAT + 7:
|
|
|
|
loc = (&c->nat4_loc)[reg - (UNW_IA64_NAT + 4)];
|
|
|
|
reg_loc = (&c->r4_loc)[reg - (UNW_IA64_NAT + 4)];
|
|
|
|
return access_nat (c, loc, reg_loc, valp, write);
|
|
|
|
|
|
|
|
|
2002-02-16 00:22:05 +01:00
|
|
|
case UNW_IA64_AR_BSP: loc = c->bsp_loc; break;
|
|
|
|
case UNW_IA64_AR_BSPSTORE: loc = c->bspstore_loc; break;
|
|
|
|
case UNW_IA64_AR_PFS: loc = c->pfs_loc; break;
|
|
|
|
case UNW_IA64_AR_RNAT: loc = c->rnat_loc; break;
|
|
|
|
case UNW_IA64_AR_UNAT: loc = c->unat_loc; break;
|
|
|
|
case UNW_IA64_AR_LC: loc = c->lc_loc; break;
|
|
|
|
case UNW_IA64_AR_FPSR: loc = c->fpsr_loc; break;
|
|
|
|
case UNW_IA64_BR + 1: loc = c->b1_loc; break;
|
|
|
|
case UNW_IA64_BR + 2: loc = c->b2_loc; break;
|
|
|
|
case UNW_IA64_BR + 3: loc = c->b3_loc; break;
|
|
|
|
case UNW_IA64_BR + 4: loc = c->b4_loc; break;
|
|
|
|
case UNW_IA64_BR + 5: loc = c->b5_loc; break;
|
|
|
|
case UNW_IA64_CFM: loc = c->cfm_loc; break;
|
|
|
|
|
|
|
|
case UNW_IA64_PR:
|
|
|
|
if (write)
|
|
|
|
{
|
2002-02-22 22:58:53 +01:00
|
|
|
c->pr = *valp; /* update the predicate cache */
|
2002-02-16 00:22:05 +01:00
|
|
|
pr = pr_ltop (c, *valp);
|
|
|
|
return ia64_put (c, c->pr_loc, pr);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ret = ia64_get (c, c->pr_loc, &pr);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
*valp = pr_ptol (c, pr);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case UNW_IA64_GR + 32 ... UNW_IA64_GR + 127: /* stacked reg */
|
|
|
|
reg = rotate_gr (c, reg - UNW_IA64_GR) + UNW_IA64_GR;
|
2002-02-22 22:58:53 +01:00
|
|
|
loc = ia64_rse_skip_regs (c->bsp, reg - (UNW_IA64_GR + 32));
|
2002-02-16 00:22:05 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
case UNW_IA64_NAT + 32 ... UNW_IA64_NAT + 127: /* stacked reg */
|
|
|
|
reg = rotate_gr (c, reg - UNW_IA64_NAT) + UNW_IA64_NAT;
|
2002-02-22 22:58:53 +01:00
|
|
|
loc = ia64_rse_skip_regs (c->bsp, reg - (UNW_IA64_NAT + 32));
|
|
|
|
nat_loc = ia64_rse_rnat_addr (loc);
|
2002-02-16 00:22:05 +01:00
|
|
|
if (nat_loc > c->rbs_top)
|
|
|
|
nat_loc = c->top_rnat_loc;
|
2002-02-22 22:58:53 +01:00
|
|
|
mask = (unw_word_t) 1 << ia64_rse_slot_num (loc);
|
2002-02-16 00:22:05 +01:00
|
|
|
return update_nat (c, nat_loc, mask, valp, write);
|
|
|
|
|
|
|
|
case UNW_IA64_AR_EC:
|
|
|
|
ret = ia64_get (c, c->cfm_loc, &cfm);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
if (write)
|
|
|
|
ret = ia64_put (c, c->cfm_loc, ((cfm & ~((unw_word_t) 0x3f << 52))
|
|
|
|
| (*valp & 0x3f) << 52));
|
|
|
|
else
|
|
|
|
*valp = (cfm >> 52) & 0x3f;
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
|
|
/* scratch & special registers: */
|
|
|
|
|
|
|
|
case UNW_IA64_GR + 0:
|
|
|
|
if (write)
|
|
|
|
return -UNW_EREADONLYREG;
|
|
|
|
*valp = 0;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case UNW_IA64_GR + 1: /* global pointer */
|
|
|
|
if (write)
|
|
|
|
return -UNW_EREADONLYREG;
|
|
|
|
*valp = c->pi.gp;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case UNW_IA64_NAT + 0:
|
|
|
|
case UNW_IA64_NAT + 1: /* global pointer */
|
|
|
|
if (write)
|
|
|
|
return -UNW_EREADONLYREG;
|
|
|
|
*valp = 0;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case UNW_IA64_NAT + 2 ... UNW_IA64_NAT + 3:
|
|
|
|
case UNW_IA64_NAT + 8 ... UNW_IA64_NAT + 31:
|
2002-02-22 22:58:53 +01:00
|
|
|
loc = ia64_scratch_loc (c, reg);
|
|
|
|
if (c->pi.flags & IA64_FLAG_SIGTRAMP)
|
|
|
|
{
|
|
|
|
mask = (unw_word_t) 1 << (reg - UNW_IA64_NAT);
|
2002-02-16 00:22:05 +01:00
|
|
|
|
2002-02-22 22:58:53 +01:00
|
|
|
ret = ia64_get (c, loc, &nat);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2002-02-16 00:22:05 +01:00
|
|
|
|
2002-02-22 22:58:53 +01:00
|
|
|
if (write)
|
|
|
|
{
|
|
|
|
if (*valp)
|
|
|
|
nat |= mask;
|
|
|
|
else
|
|
|
|
nat &= ~mask;
|
|
|
|
ret = ia64_put (c, loc, nat);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
*valp = (nat & mask) != 0;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
break;
|
2002-02-16 00:22:05 +01:00
|
|
|
|
2002-02-22 22:58:53 +01:00
|
|
|
case UNW_IA64_GR + 15 ... UNW_IA64_GR + 18:
|
|
|
|
if (c->pi.flags & IA64_FLAG_SIGTRAMP)
|
|
|
|
loc = ia64_scratch_loc (c, reg);
|
|
|
|
else
|
2002-02-16 00:22:05 +01:00
|
|
|
{
|
2002-02-22 22:58:53 +01:00
|
|
|
if (write)
|
|
|
|
c->eh_args[reg - (UNW_IA64_GR + 15)] = *valp;
|
2002-02-16 00:22:05 +01:00
|
|
|
else
|
2002-02-22 22:58:53 +01:00
|
|
|
*valp = c->eh_args[reg - (UNW_IA64_GR + 15)] = *valp;
|
|
|
|
return 0;
|
2002-02-16 00:22:05 +01:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2002-02-22 22:58:53 +01:00
|
|
|
case UNW_IA64_GR + 2 ... UNW_IA64_GR + 3:
|
|
|
|
case UNW_IA64_GR + 8 ... UNW_IA64_GR + 14:
|
|
|
|
case UNW_IA64_GR + 19 ... UNW_IA64_GR + 31:
|
|
|
|
case UNW_IA64_BR + 0:
|
|
|
|
case UNW_IA64_BR + 7:
|
|
|
|
case UNW_IA64_AR_RSC:
|
2002-02-16 00:22:05 +01:00
|
|
|
case UNW_IA64_AR_25:
|
|
|
|
case UNW_IA64_AR_26:
|
|
|
|
case UNW_IA64_AR_CCV:
|
2002-02-22 22:58:53 +01:00
|
|
|
loc = ia64_scratch_loc (c, reg);
|
2002-02-16 00:22:05 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
dprintf ("%s: bad register number %d\n", __FUNCTION__, reg);
|
|
|
|
return -UNW_EBADREG;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (write)
|
|
|
|
{
|
|
|
|
if (readonly)
|
|
|
|
return -UNW_EREADONLYREG;
|
|
|
|
return ia64_put (c, loc, *valp);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
return ia64_get (c, loc, valp);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ia64_access_fpreg (struct ia64_cursor *c, int reg, unw_fpreg_t *valp,
|
|
|
|
int write)
|
|
|
|
{
|
|
|
|
unw_word_t loc = -8, flags, tmp_loc;
|
|
|
|
int ret, i;
|
|
|
|
|
|
|
|
switch (reg)
|
|
|
|
{
|
|
|
|
case UNW_IA64_FR + 0:
|
|
|
|
if (write)
|
|
|
|
return -UNW_EREADONLYREG;
|
|
|
|
*valp = unw.f0;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case UNW_IA64_FR + 1:
|
|
|
|
if (write)
|
|
|
|
return -UNW_EREADONLYREG;
|
|
|
|
|
|
|
|
if (c->pi.flags & IA64_FLAG_BIG_ENDIAN)
|
|
|
|
*valp = unw.f1_be;
|
|
|
|
else
|
|
|
|
*valp = unw.f1_le;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case UNW_IA64_FR + 2: loc = c->f2_loc; break;
|
|
|
|
case UNW_IA64_FR + 3: loc = c->f3_loc; break;
|
|
|
|
case UNW_IA64_FR + 4: loc = c->f4_loc; break;
|
|
|
|
case UNW_IA64_FR + 5: loc = c->f5_loc; break;
|
|
|
|
case UNW_IA64_FR + 16 ... UNW_IA64_FR + 31:
|
|
|
|
loc = c->fr_loc[reg - (UNW_IA64_FR + 16)];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case UNW_IA64_FR + 6 ... UNW_IA64_FR + 15:
|
2002-02-22 22:58:53 +01:00
|
|
|
loc = ia64_scratch_loc (c, reg);
|
2002-02-16 00:22:05 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
case UNW_IA64_FR + 32 ... UNW_IA64_FR + 127:
|
2002-02-22 22:58:53 +01:00
|
|
|
if (c->pi.flags & IA64_FLAG_SIGTRAMP)
|
2002-02-16 00:22:05 +01:00
|
|
|
{
|
2002-02-22 22:58:53 +01:00
|
|
|
ret = ia64_get (c, c->sp + 0x10 + SIGFRAME_ARG2_OFF, &loc);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
ret = ia64_get (c, loc + SIGCONTEXT_FLAGS_OFF, &flags);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (!(flags & IA64_SC_FLAG_FPH_VALID))
|
2002-02-16 00:22:05 +01:00
|
|
|
{
|
2002-02-22 22:58:53 +01:00
|
|
|
if (write)
|
2002-02-16 00:22:05 +01:00
|
|
|
{
|
2002-02-22 22:58:53 +01:00
|
|
|
/* initialize fph partition: */
|
|
|
|
tmp_loc = loc + SIGCONTEXT_FR_OFF + 32*16;
|
|
|
|
for (i = 32; i < 128; ++i, tmp_loc += 16)
|
|
|
|
{
|
|
|
|
ret = ia64_putfp (c, tmp_loc, unw.f0);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
/* mark fph partition as valid: */
|
|
|
|
ret = ia64_put (c, loc + SIGCONTEXT_FLAGS_OFF,
|
|
|
|
flags | IA64_SC_FLAG_FPH_VALID);
|
2002-02-16 00:22:05 +01:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
2002-02-22 22:58:53 +01:00
|
|
|
else
|
|
|
|
{
|
|
|
|
*valp = unw.f0;
|
|
|
|
return 0;
|
|
|
|
}
|
2002-02-16 00:22:05 +01:00
|
|
|
}
|
|
|
|
}
|
2002-02-22 22:58:53 +01:00
|
|
|
reg = rotate_fr (c, reg - UNW_IA64_FR) + UNW_IA64_FR;
|
|
|
|
loc = ia64_scratch_loc (c, reg);
|
2002-02-16 00:22:05 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (write)
|
|
|
|
return ia64_putfp (c, loc, *valp);
|
|
|
|
else
|
|
|
|
return ia64_getfp (c, loc, valp);
|
|
|
|
}
|