<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;">\section{Evaluation on Palmed}\label{sec:a40_eval}

To evaluate the gain brought by each frontend model, we plug them successively
on top of the \palmed{} backend model. The number of cycles for a kernel
$\kerK$ is then predicted as the maximum between the backend-predicted time and
the frontend-predicted time.

We evaluate four models: \palmed{}'s backend alone, \palmed{} with a purely
linear frontend, based on our modeled number of \uops{} for each instruction,
\palmed{} with the no-cross frontend, and finally \palmed{} with the
dispatch-queues frontend. The results of each model are reported in
\autoref{table:a72_frontend_err}, to which we add \llvmmca{}'s results as a
basis for comparison with the state-of-the-art.

\begin{table}
    \centering
    \begin{tabular}{l l c r r r r r}
        \toprule
        &amp; &amp; &amp; \multirow{2}{*}{\llvmmca{}} &amp; \multicolumn{4}{c}{\palmed{} with
        frontend\ldots} \\
        &amp; &amp; &amp; &amp; none &amp; linear &amp; no-cross &amp; disp.\ queues \\
        \midrule{}
        \multirow{3}{*}{SPEC} &amp; \covrow{} &amp; 100.0 &amp; \na{} &amp; 97.21 &amp; 97.21 &amp; 97.16 \\
                              &amp; \errrow{} &amp; 9.0 &amp; 20.1 &amp; 6.2 &amp; 6.3 &amp; 4.6 \\
                              &amp; \taurow{} &amp; 0.83 &amp; 0.88 &amp; 0.91 &amp; 0.91 &amp; 0.93 \\
        \midrule
        \multirow{3}{*}{Polybench} &amp; \covrow{} &amp; 100.00 &amp; \na{} &amp; 99.33 &amp; 99.33 &amp; 99.33 \\
                                   &amp; \errrow{} &amp; 13.9 &amp; 12.6 &amp; 8.1 &amp; 8.1 &amp; 8.0 \\
                                   &amp; \taurow{} &amp; 0.47 &amp; 0.82 &amp; 0.88 &amp; 0.88 &amp; 0.90 \\
        \bottomrule
    \end{tabular}
    \caption{Comparative accuracy of IPC predictions with different frontend
    models on the Cortex A72}\label{table:a72_frontend_err}
\end{table}

As expected, the error is greatly reduced with the addition of any reasonable
frontend model ---~especially on the SPEC benchmark suite. Using the
dispatch-queues model, which models more accurately the frontend, further
reduces significantly the error rate on SPEC by 1.6 points, without
significantly increasing the $\tau_K$ coefficient. On Polybench, however, the
gains brought by the dispatch-queues model are very modest ---~only 0.1 point.

In all cases, \palmed{} with a frontend model performs significantly better
than \llvmmca{} on the Cortex A72.
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