The state-of-the-art tools presented in \autoref{sec:sota} are already capable
of good microarchitectural analysis and predictions in many aspects. One thing,
however, that we found lacking, was a generic method to obtain a model for a
given microarchitecture. Indeed, while \eg{} \iaca{} and \uopsinfo{} are
performant and quite exhaustive models of Intel's x86-64 implementations, they
are restricted to Intel CPUs ---~and few others for \uopsinfo{}. These models
were, at least up to a point, handcrafted. While \iaca{} is based on insider's
knowledge from Intel (and thus would not work for \eg{} AMD), \uopsinfo{}'s
method is based on specific hardware counters and handpicked instructions with
specific properties.

While these methods provide great models, they only apply to the covered CPUs.
In the meantime, many new CPUs are released, some for commercial applications,
some others for specific domains, fostering less attention from
microarchitecture specialists. For those CPUs not covered by these specific
models, a generic method to extract a model from running benchmarks on a
processor could be beneficial to performance debuggers.

While \pmevo{}~\cite{PMEvo} laid a first milestone in this direction (see
\autoref{sec:sota}), their methodology struggles to scale to the full
instruction set of a CPU, as we show in this chapter. To this end,
\nderumig{} designed \palmed{} during his PhD work. Although the theoretical
work at the core of \palmed{} is his, I contributed significantly to this
project during the first period of my own PhD.

In this chapter, sections~\ref{sec:palmed_resource_models}
through~\ref{sec:palmed_pipedream} describe \palmed{}, and present what is
mostly not my own work, but introduce important concepts for this manuscript.
Sections~\ref{sec:benchsuite_bb} and later describe my own work on this
project.
