[
    {
        "EventCode": "0x54",
        "UMask": "0x1",
        "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.ABORT_CONFLICT",
        "PublicDescription": "Number of times a TSX line had a cache conflict.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x2",
        "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.ABORT_CAPACITY",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x4",
        "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
        "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x8",
        "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
        "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x10",
        "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
        "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x20",
        "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
        "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "UMask": "0x40",
        "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
        "Counter": "0,1,2,3",
        "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
        "PublicDescription": "Number of times we could not allocate Lock Buffer.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5d",
        "UMask": "0x1",
        "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
        "Counter": "0,1,2,3",
        "EventName": "TX_EXEC.MISC1",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5d",
        "UMask": "0x2",
        "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
        "Counter": "0,1,2,3",
        "EventName": "TX_EXEC.MISC2",
        "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5d",
        "UMask": "0x4",
        "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
        "Counter": "0,1,2,3",
        "EventName": "TX_EXEC.MISC3",
        "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5d",
        "UMask": "0x8",
        "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
        "Counter": "0,1,2,3",
        "EventName": "TX_EXEC.MISC4",
        "PublicDescription": "RTM region detected inside HLE.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5d",
        "UMask": "0x10",
        "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
        "Counter": "0,1,2,3",
        "EventName": "TX_EXEC.MISC5",
        "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "UMask": "0x10",
        "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "UMask": "0x10",
        "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
        "CounterMask": "1",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "UMask": "0x10",
        "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
        "CounterMask": "6",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA3",
        "UMask": "0x2",
        "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
        "CounterMask": "2",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA3",
        "UMask": "0x6",
        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
        "Counter": "0,1,2,3",
        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
        "CounterMask": "6",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB0",
        "UMask": "0x10",
        "BriefDescription": "Demand Data Read requests who miss L3 cache",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
        "PublicDescription": "Demand Data Read requests who miss L3 cache.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC3",
        "UMask": "0x2",
        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
        "Counter": "0,1,2,3",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "Errata": "SKL089",
        "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC8",
        "UMask": "0x1",
        "BriefDescription": "Number of times an HLE execution started.",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.START",
        "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC8",
        "UMask": "0x2",
        "BriefDescription": "Number of times an HLE execution successfully committed",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.COMMIT",
        "PublicDescription": "Number of times HLE commit succeeded.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC8",
        "UMask": "0x4",
        "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.ABORTED",
        "PublicDescription": "Number of times HLE abort was triggered. (PEBS)",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC8",
        "UMask": "0x8",
        "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.ABORTED_MEM",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC8",
        "UMask": "0x10",
        "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.ABORTED_TIMER",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC8",
        "UMask": "0x20",
        "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC8",
        "UMask": "0x40",
        "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
        "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC8",
        "UMask": "0x80",
        "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
        "Counter": "0,1,2,3",
        "EventName": "HLE_RETIRED.ABORTED_EVENTS",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC9",
        "UMask": "0x1",
        "BriefDescription": "Number of times an RTM execution started.",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.START",
        "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC9",
        "UMask": "0x2",
        "BriefDescription": "Number of times an RTM execution successfully committed",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.COMMIT",
        "PublicDescription": "Number of times RTM commit succeeded.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC9",
        "UMask": "0x4",
        "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ",
        "PEBS": "1",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.ABORTED",
        "PublicDescription": "Number of times RTM abort was triggered. (PEBS)",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC9",
        "UMask": "0x8",
        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.ABORTED_MEM",
        "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC9",
        "UMask": "0x10",
        "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.ABORTED_TIMER",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC9",
        "UMask": "0x20",
        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
        "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC9",
        "UMask": "0x40",
        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
        "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC9",
        "UMask": "0x80",
        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
        "Counter": "0,1,2,3",
        "EventName": "RTM_RETIRED.ABORTED_EVENTS",
        "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles.",
        "PEBS": "2",
        "MSRValue": "0x4",
        "Counter": "0,1,2,3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
        "MSRIndex": "0x3F6",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
        "TakenAlone": "1",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles.",
        "PEBS": "2",
        "MSRValue": "0x8",
        "Counter": "0,1,2,3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
        "MSRIndex": "0x3F6",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
        "TakenAlone": "1",
        "SampleAfterValue": "50021",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles.",
        "PEBS": "2",
        "MSRValue": "0x10",
        "Counter": "0,1,2,3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
        "MSRIndex": "0x3F6",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
        "TakenAlone": "1",
        "SampleAfterValue": "20011",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles.",
        "PEBS": "2",
        "MSRValue": "0x20",
        "Counter": "0,1,2,3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
        "MSRIndex": "0x3F6",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
        "TakenAlone": "1",
        "SampleAfterValue": "100007",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles.",
        "PEBS": "2",
        "MSRValue": "0x40",
        "Counter": "0,1,2,3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
        "MSRIndex": "0x3F6",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
        "TakenAlone": "1",
        "SampleAfterValue": "2003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles.",
        "PEBS": "2",
        "MSRValue": "0x80",
        "Counter": "0,1,2,3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
        "MSRIndex": "0x3F6",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
        "TakenAlone": "1",
        "SampleAfterValue": "1009",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles.",
        "PEBS": "2",
        "MSRValue": "0x100",
        "Counter": "0,1,2,3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
        "MSRIndex": "0x3F6",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
        "TakenAlone": "1",
        "SampleAfterValue": "503",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xCD",
        "UMask": "0x1",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles.",
        "PEBS": "2",
        "MSRValue": "0x200",
        "Counter": "0,1,2,3",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
        "MSRIndex": "0x3F6",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
        "TakenAlone": "1",
        "SampleAfterValue": "101",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts demand data reads that miss in the L3.",
        "MSRValue": "0x3fbc000001 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts demand data reads that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc00001 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc00001 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc00001 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b800001 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604000001 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.",
        "MSRValue": "0x3fbc000002 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand data writes (RFOs) that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc00002 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc00002 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc00002 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b800002 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604000002 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand code reads that miss in the L3.",
        "MSRValue": "0x3fbc000004 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand code reads that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc00004 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc00004 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc00004 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b800004 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604000004 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.",
        "MSRValue": "0x3fbc000010 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc00010 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc00010 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc00010 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b800010 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604000010 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.",
        "MSRValue": "0x3fbc000020 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc00020 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc00020 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc00020 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b800020 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604000020 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.",
        "MSRValue": "0x3fbc000080 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc00080 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc00080 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc00080 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b800080 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604000080 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.",
        "MSRValue": "0x3fbc000100 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc00100 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc00100 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc00100 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b800100 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604000100 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.",
        "MSRValue": "0x3fbc000400 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc00400 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc00400 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc00400 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b800400 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604000400 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts any other requests that miss in the L3.",
        "MSRValue": "0x3fbc008000 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts any other requests that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts any other requests that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc08000 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts any other requests that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts any other requests that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc08000 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts any other requests that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts any other requests that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc08000 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts any other requests that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts any other requests that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b808000 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts any other requests that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts any other requests that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604008000 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts any other requests that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch data reads that miss in the L3.",
        "MSRValue": "0x3fbc000490 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch data reads that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc00490 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc00490 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc00490 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b800490 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604000490 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch RFOs that miss in the L3.",
        "MSRValue": "0x3fbc000120 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch RFOs that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc00120 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc00120 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc00120 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b800120 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604000120 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.",
        "MSRValue": "0x3fbc000491 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch data reads that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc00491 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc00491 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc00491 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b800491 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604000491 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.",
        "MSRValue": "0x3fbc000122 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch RFOs that miss in the L3. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
        "MSRValue": "0x083fc00122 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
        "MSRValue": "0x103fc00122 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
        "MSRValue": "0x063fc00122 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.",
        "MSRValue": "0x063b800122 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Offcore": "1",
        "EventCode": "0xB7, 0xBB",
        "UMask": "0x1",
        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.",
        "MSRValue": "0x0604000122 ",
        "Counter": "0,1,2,3",
        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3"
    }
]