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297 lines
8.5 KiB
Groff
297 lines
8.5 KiB
Groff
'\" t
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.\" Manual page created with latex2man on Fri Jan 17 15:46:04 PST 2003
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.\" NOTE: This file is generated, DO NOT EDIT.
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.de Vb
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.ft CW
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..
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.de Ve
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.ft R
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.fi
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..
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.TH "LIBUNWIND\-IA64" "3" "17 January 2003" "Programming Library " "Programming Library "
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.SH NAME
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libunwind\-ia64 \-\- IA\-64\-specific support in libunwind
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.PP
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.SH INTRODUCTION
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.PP
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The IA\-64 version of libunwind
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uses a platform\-string of
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ia64
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and, at least in theory, should be able to support all
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operating systems adhering to the processor\-specific ABI defined for
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the Itanium Processor Family. This includes both little\-endian Linux
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and big\-endian HP\-UX. Furthermore, to make it possible for a single
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library to unwind both 32\- and 64\-bit targets, the type
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unw_word_t
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is always defined to be 64 bits wide (independent
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of the natural word\-size of the host). Having said that, the current
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implementation has been tested only with IA\-64 Linux.
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.PP
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When targeting IA\-64, the libunwind
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header file defines the
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macro UNW_TARGET_IA64
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as 1 and the macro UNW_TARGET
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as ``ia64\&'' (without the quotation marks). The former makes it
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possible for platform\-dependent unwind code to use
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conditional\-compilation to select an appropriate implementation. The
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latter is useful for stringification purposes and to construct
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target\-platform\-specific symbols.
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.PP
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One special feature of IA\-64 is the use of NaT bits to support
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speculative execution. Often, NaT bits are thought of as the ``65\-th
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bit\&'' of a general register. However, to make everything fit into
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64\-bit wide unw_word_t
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values, libunwind
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treats the
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NaT\-bits like separate boolean registers, whose 64\-bit value is either
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TRUE (non\-zero) or FALSE (zero).
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.PP
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.SH MACHINE\-STATE
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.PP
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The machine\-state (set of registers) that is accessible through
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libunwind
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depends on the type of stack frame that a cursor
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points to. For normal frames, all ``preserved\&'' (callee\-saved)
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registers are accessible. For signal\-trampoline frames, all registers
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(including ``scratch\&'' (caller\-saved) registers) are accessible. Most
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applications do not have to worry a\-priori about which registers are
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accessible when. In case of doubt, it is always safe to \fItry\fP
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to
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access a register (via unw_get_reg()
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or
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unw_get_fpreg())
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and if the register isn\&'t accessible, the
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call will fail with a return\-value of \-UNW_EBADREG\&.
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.PP
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As a special exception to the above general rule, scratch registers
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r15\-r18
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are always accessible, even in normal
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frames. This makes it possible to pass arguments, e.g., to exception
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handlers.
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.PP
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For a detailed description of the IA\-64 register usage convention,
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please see the ``Itanium Software Conventions and Runtime Architecture
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Guide\&'', available at:
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.ce 100
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\fBhttp://www.intel.com/design/itanium/downloads/245358.htm\fP
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.ce 0
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.PP
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.SH REGISTER NAMES
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.PP
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The IA\-64\-version of libunwind
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defines three kinds of register
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name macros: frame\-register macros, normal register macros, and
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convenience macros. Below, we describe each kind in turn:
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.PP
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.SS FRAME\-REGISTER MACROS
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.PP
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Frame\-registers are special (pseudo) registers because they always
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have a valid value, even though sometimes they do not get saved
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explicitly (e.g., if a memory stack frame is 16 bytes in size, the
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previous stack\-pointer value can be calculated simply as
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sp+16,
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so there is no need to save the stack\-pointer
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explicitly). Moreover, the set of frame register values uniquely
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identifies a stack frame. The IA\-64 architecture defines two stacks
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(a memory and a register stack). Including the instruction\-pointer
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(IP), this means there are three frame registers:
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.TP
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UNW_IA64_IP:
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Contains the instruction pointer (IP, or
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``program counter\&'') of the current stack frame. Given this value,
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the remaining machine\-state corresponds to the register\-values that
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were present in the CPU when it was just about to execute the
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instruction pointed to by UNW_IA64_IP\&.
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Bits 0 and 1 of
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this frame\-register encode the slot number of the instruction.
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\fBNote:\fP
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Due to the way the call instruction works on IA\-64,
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the slot number is usually zero, but can be non\-zero, e.g., in the
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stack\-frame of a signal\-handler trampoline.
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.TP
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UNW_IA64_SP:
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Contains the (memory) stack\-pointer
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value (SP). This frame\-register is read\-only.
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.TP
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UNW_IA64_BSP:
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Contains the register backing\-store
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pointer (BSP). This frame\-register is read\-only. \fBNote:\fP
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the value in this register is equal to the contents of register
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ar.bsp
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at the time the instruction at UNW_IA64_IP
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was about to begin execution.
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.PP
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.SS NORMAL REGISTER MACROS
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.PP
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The following normal register name macros are available:
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.TP
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UNW_IA64_GR:
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The base\-index for general (integer)
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registers. Add an index in the range from 0..127 to get a
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particular general register. For example, to access r4,
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the index UNW_IA64_GR+4
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should be used. Register
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r0
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is read\-only, and any attempt to write to index
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UNW_IA64_GR+0
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will result in an error
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(\-UNW_EREADONLYREG).
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.TP
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UNW_IA64_NAT:
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The base\-index for the NaT bits of the
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general (integer) registers. A non\-zero value in these registers
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corresponds to a set NaT\-bit. Add an index in the range from 0..127
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to get a particular NaT\-bit register. For example, to access the
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NaT bit of r4,
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the index UNW_IA64_NAT+4
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should be used.
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.TP
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UNW_IA64_FR:
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The base\-index for floating\-point
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registers. Add an index in the range from 0..127 to get a
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particular floating\-point register. For example, to access
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f2,
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the index UNW_IA64_FR+2
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should be
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used. Registers f0
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and f1
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are read\-only, and any
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attempt to write to indices UNW_IA64_FR+0
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or
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UNW_IA64_FR+1
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will result in an error
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(\-UNW_EREADONLYREG).
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.TP
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UNW_IA64_AR:
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The base\-index for application
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registers. Add an index in the range from 0..127 to get a
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particular application register. For example, to access
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ar40,
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the index UNW_IA64_AR+40
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should be
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used. The IA\-64 architecture defines several application registers
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as ``reserved for future use\&''\&. Attempting to access such registers
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results in an error (\-UNW_EBADREG).
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.TP
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UNW_IA64_BR:
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The base\-index for branch registers.
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Add an index in the range from 0..7 to get a particular branch
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register. For example, to access b6,
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the index
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UNW_IA64_BR+6
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should be used.
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.TP
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UNW_IA64_PR:
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Contains the set of predicate registers.
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This 64\-bit wide register contains registers p0
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through
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p63
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in the ``broad\-side\&'' format (i.e., p0
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corresponds to bit 0, p1
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to bit 1, and so on).
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.TP
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UNW_IA64_CFM:
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Contains the current\-frame\-mask
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register.
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.PP
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.SS CONVENIENCE MACROS
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.PP
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Convenience macros are simply aliases for certain frequently used
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registers:
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.TP
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UNW_IA64_GP:
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Alias for UNW_IA64_GR+1\&.
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The global\-pointer register. For unwinding\-purposes, this register
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is treated as read\-only.
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.TP
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UNW_IA64_TP:
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Alias for UNW_IA64_GR+13\&.
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The thread\-pointer register. For unwinding\-purposes, this register is
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treated as read\-only.
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.TP
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UNW_IA64_AR_RSC:
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Alias for UNW_IA64_GR+16\&.
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The register\-stack configuration register.
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.TP
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UNW_IA64_AR_BSP:
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Alias for
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UNW_IA64_GR+17\&.
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This register index accesses the
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value of register ar.bsp
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as of the time it was last saved
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explicitly. This is rarely what you want. Normally, you\&'ll want to
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use UNW_IA64_BSP
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instead.
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.TP
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UNW_IA64_AR_BSPSTORE:
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Alias for UNW_IA64_GR+18\&.
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The register\-backing store write pointer.
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.TP
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UNW_IA64_AR_RNAT:
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Alias for UNW_IA64_GR+19\&.
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The register\-backing store NaT\-collection register.
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.TP
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UNW_IA64_AR_CCV:
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Alias for UNW_IA64_GR+32\&.
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The compare\-and\-swap value register.
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.TP
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UNW_IA64_AR_UNAT:
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Alias for UNW_IA64_GR+36\&.
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The user NaT\-collection register.
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.TP
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UNW_IA64_AR_FPSR:
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Alias for UNW_IA64_GR+40\&.
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The floating\-point status (and control) register.
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.TP
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UNW_IA64_AR_PFS:
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Alias for UNW_IA64_GR+64\&.
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The previous frame\-state register.
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.TP
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UNW_IA64_AR_LC:
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Alias for UNW_IA64_GR+65\&.
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The loop\-count register.
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.TP
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UNW_IA64_AR_EC:
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Alias for UNW_IA64_GR+66\&.
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The epilogue\-count register.
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.PP
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.SH THE UNWIND\-CONTEXT TYPE
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.PP
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On IA\-64, unw_context_t
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is simply an alias for
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ucontext_t
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(as defined by the Single UNIX Spec). This implies
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that it is possible to initialize a value of this type not just with
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unw_getcontext(),
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but also with getcontext(),
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for
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example. However, since this is an IA\-64\-specific extension to
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libunwind,
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portable code should not rely on this equivalence.
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.PP
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.SH SEE ALSO
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.PP
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libunwind(3)
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.PP
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.SH AUTHOR
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.PP
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David Mosberger\-Tang
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.br
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Hewlett\-Packard Labs
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.br
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Palo\-Alto, CA 94304
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.br
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Email: \fBdavidm@hpl.hp.com\fP
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.br
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WWW: \fBhttp://www.hpl.hp.com/research/linux/libunwind/\fP\&.
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.\" NOTE: This file is generated, DO NOT EDIT.
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